EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
MPN: EPM9560RC304-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $78 | $780.00 |
| 100 | $70 | $7,000.00 |
| 500 | $62 | $31,000.00 |
| 1,000 | $55 | $55,000.00 |
Drop-in alternatives for EPM9560RC304-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC304-10
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$17.6 / Unit
View Datasheet →EPM9560RC304-15
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$9.4 / Unit
View Datasheet →EPM9560RC304-15N
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$19.8 / Unit
View Datasheet →EPM9560RC304-20N
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View Datasheet →EPM9560RC304-15C
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$24.5 / Unit
View Datasheet →EPM9560RC304-15F
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$18.75 / Unit
View Datasheet →EPM9560RC304-2 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (EPLD - Erasable PLD) |
| Usable Gates | Approximately 12,000 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins | 304 |
| Package | 304-pin RQFP (RC) |
| Speed Grade | -2 |
| Core Supply Voltage | 5.0 V |
| I/O Supply Voltage | 5.0 V |
| Programming Technology | EEPROM (in-system programmable) |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) |
| Operating Temperature | Commercial (0C to +70C) |
| Mounting Type | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Configuration Memory | On-chip EEPROM (non-volatile) |
EPM9560RC304-2 Pin Configuration
| Pin 1 | I/O — User I/O pin (function per design) |
| Pin 76 | I/O — User I/O pin (function per design) |
| Pin 77 | GND — Ground |
| Pin 78 | I/O — User I/O pin (function per design) |
| Pin 151 | I/O — User I/O pin (function per design) |
| Pin 152 | VCC — +5.0 V core supply |
| Pin 153 | I/O — User I/O pin (function per design) |
| Pin 227 | I/O — User I/O pin (function per design) |
| Pin 228 | GND — Ground |
| Pin 229 | I/O — User I/O pin (function per design) |
| Pin 302 | TDI — JTAG Test Data In |
| Pin 303 | TMS — JTAG Test Mode Select |
| Pin 304 | TCK — JTAG Test Clock |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC304-2 is suitable for 6 applications: 5 V System Glue Logic, Address Decoding & Memory Interfacing, Bus Interface Bridging, State Machine Controllers, Legacy Telecom Backplane Glue, Peripheral Aggregation Front-End.
5 V System Glue Logic
The EPM9560RC304-2 is purpose-built for 5 V system glue logic with 304 user I/O pins and 12,000 usable gates, ideal for legacy microprocessor and microcontroller boards. The 5.0 V tolerant I/Os directly interface with TTL and CMOS 5 V peripherals without level shifters, eliminating BOM cost and signal-delay penalties. Compared to modern 3.3 V CPLDs, the EPM9560RC304-2 simplifies designs in industrial 5 V backplanes, factory automation controllers, and legacy telecom equipment where 5 V rails are mandatory. The on-chip EEPROM configuration provides instant-on behavior at power-up, critical for boot-time-critical systems.
Recommended
Address Decoding & Memory Interfacing
With 304 user I/O and 16 LABs of MAX architecture, the EPM9560RC304-2 delivers wide address decoding and memory-interface glue for 32-bit and 64-bit microprocessor systems. The deterministic timing of CPLD logic ensures zero-wait-state address decoding for SRAM, DRAM, and flash banks. The -2 speed grade is sufficient for systems with clock rates up to ~50 MHz. The JTAG ISP interface allows field upgrades of the decoding map without removing the device from the production PCB, supporting late-stage memory-map revisions and field reconfiguration.
Recommended
Bus Interface Bridging
The EPM9560RC304-2 serves as a bridge between legacy parallel buses (ISA, VME, PCI-5V) and modern processors, with 304 I/O supporting wide parallel capture and re-transmission. The 5.0 V PCI-compatible drive strength meets the PCI 5 V signaling specification without external buffers. The CPLD's deterministic propagation delay supports bus-to-bus turn-around timing without metastability risks. This application benefits particularly from the on-chip EEPROM, which retains the bridge configuration across power cycles and reduces system boot time.
Recommended
State Machine Controllers
The EPM9560RC304-2's 16 LABs each containing 16 macrocells provide abundant registered logic for complex state-machine controllers in industrial automation. Each macrocell offers configurable register clock, clear, and preset signals, enabling precise control sequencing of motors, valves, and actuators. The -2 speed grade's slower propagation delay is acceptable for most mechanical control loops (typically < 1 kHz update rates) and provides cost savings compared to -15 or -20 grades. The 304 I/O support hundreds of sensor inputs and actuator outputs per device.
Recommended
Legacy Telecom Backplane Glue
The EPM9560RC304-2 is widely deployed in legacy telecom backplanes for T1/E1, ISDN, and channel-bank aggregation functions where 5 V rails remain standard. The 304 I/O supports backplane connector aggregation, link-status LED driving, and alarm-collection logic in a single device. The IEEE 1149.1 JTAG interface enables in-system boundary-scan test of the entire backplane, critical for manufacturing test and field diagnostics. The non-volatile EEPROM configuration means no external boot PROM is required, simplifying the backplane BOM.
Recommended
Peripheral Aggregation Front-End
The EPM9560RC304-2 aggregates slow-speed peripherals (UARTs, parallel I/O, keypad scanners, character LCDs) into a single fast bus to the host processor. With 304 user I/O, a single EPM9560RC304-2 can replace dozens of 74-series glue-logic packages, reducing PCB area and improving reliability. The instant-on behavior from EEPROM configuration means peripherals are ready immediately at system reset. The 5 V tolerant I/O drives character LCDs, keypads, and optocouplers directly without level shifters, reducing total system cost.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC304-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC304-10 | EPM9560RC304-15 | EPM9560RC304-15N | EPM9560RC304-20N | EPM9560RC304-15C | EPM9560RC304-15F |
|---|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 304-pin RQFP (RC) | 304-pin RQFP (RC) - same | 304-pin RQFP (RC) - same | 304-pin RQFP (RC) - same | 304-pin RQFP (RC) - same | 304-pin RQFP (RC) - same | 304-pin RQFP (RC) - same |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Speed Grade | -2 (slowest) | -10 (5x faster) | -15 (7.5x faster) | -15 (7.5x faster) | -20 (10x faster) | -15 (7.5x faster) | -15 (7.5x faster) |
| Core Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| User I/O | 304 | 304 | 304 | 304 | 304 | 304 | 304 |
| RoHS Compliance | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | Yes (N suffix) | Yes (N suffix) | [DATA_NEEDED] | Yes (F suffix indicates lead-free) |
Key Differentiators
- Highest gate-count MAX 9000 in 304-pin RQFP with slowest speed grade (vs EPM9560RC304-10)
- 304 user I/O in a single CPLD (vs EPM9560ARI240-10)
- On-chip EEPROM with ISP via JTAG (vs Modern MAX II EPM1270)
Design Notes
Decouple each EPM9560RC304-2 VCC pin pair with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus one bulk 10-47 uF tantalum or aluminum polymer capacitor near the device. The MAX 9000 family draws transient current during simultaneous I/O switching; insufficient decoupling causes VCC droop that propagates as ground bounce into adjacent logic. For 304-pin RQFP, place 8-10 VCC/GND pin pairs worth of decoupling (one cap per pair) across the package perimeter.
The -2 speed grade is the slowest of the EPM9560 family and may fail timing in designs that previously used -10 or -15. Estimated: at 5 V and 25C, the -2 tPD is roughly 25 ns (5x the -10 grade's 5 ns). For designs migrating from -10/-15 down to -2 for cost savings, re-run static timing analysis on all paths to confirm setup/hold margins are still met. Pinout is identical across speed grades, so PCB layout is unchanged.
The 304-pin RQFP package has 304 simultaneous-switching I/Os, creating significant SSO (simultaneous-switching output) noise on the internal VCC/GND rails. Estimate: at full 304-I/O toggle, expect 200-400 mV of SSO noise without proper decoupling. Limit simultaneous switching to groups of 8-16 I/O at a time by using staggered clock enables in the design. The MAX 9000 PCI-compatible drive strength helps mitigate this but does not eliminate it.
The 304-pin RQFP package has a junction-to-ambient thermal resistance (theta_JA) of approximately 25 C/W with still air. At maximum toggle activity (all 304 I/O at 10 MHz, 5.0 V), the EPM9560RC304-2 dissipates roughly 1.5-2 W. For high-activity designs, ensure at least 4 square inches of copper pour on the top layer directly under the package for heat spreading. Forced-air cooling extends the operating temperature range for industrial applications.
Compliance Information
Original Altera MAX 9000 family pre-dates widespread RoHS adoption; lead-free variants are designated with N suffix (e.g., EPM9560RC304-15N). Standard -2 grade RoHS status not stated in verified data; verify with manufacturer datasheet before use in RoHS-required designs.
