EPM9560RC30415 vs EPM9560RC304-10 Comparison
Detailed side-by-side comparison of EPM9560RC30415 by Intel and EPM9560RC304-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC30415 | EPM9560RC304-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD / EPLD |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | — |
| Usable Gates | 12,000 | 16000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 (40 macro cells each) | — |
| User I/O Pins | 360 | 304 (package-limited) |
| Pin Count | 304 | 304 |
| Package | 304-RQFP (Power Quad Flat Pack) | RQFP-304 (RC) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | -10 |
| Maximum Internal Frequency | 117.6 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Technology | CMOS EEPROM | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Macrocells | — | 560 |
| Logic Elements | — | 560 |
| Pin-to-Pin Propagation Delay | — | 12 ns |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Method | — | JTAG in-system (ISP) |
| Process Technology | — | 0.65 µm CMOS EEPROM |
| MSL Level | — | 3 (168 Hours) |