EPM9560RC30415 vs EPM9560RC304-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC30415 sa pamamagitan ng Intel at EPM9560RC304-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC30415 | EPM9560RC304-10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD / EPLD |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | — |
| Usable Gates | 12,000 | 16000 |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 (40 macro cells each) | — |
| User I/O Pins | 360 | 304 (package-limited) |
| Bilang ng Pin | 304 | 304 |
| Packhaging | 304-RQFP (Power Quad Flat Pack) | RQFP-304 (RC) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | -10 |
| Maximum Internal Frequency | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Technology | CMOS EEPROM | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Macrocells | — | 560 |
| Logic Elements | — | 560 |
| Pin-to-Pin Propagation Delay | — | 12 ns |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Method | — | JTAG in-system (ISP) |
| Process Technology | — | 0.65 µm CMOS EEPROM |
| Level ng MSL | — | 3 (168 Hours) |