EPM9560RI208-20 vs EPM9560RI208-15N Comparison
Detailed side-by-side comparison of EPM9560RI208-20 by Intel and EPM9560RI208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-20 | EPM9560RI208-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX), 3rd generation |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| Package | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Operating Temperature | [DATA_NEEDED: operating temperature range grade] | 0C to 70C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Mounting Type | Surface Mount | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Configuration Memory | — | CMOS EEPROM, in-system programmable |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Supply Voltage | — | 5.0 V |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |
| Programming Interface | — | IEEE 1149.1 JTAG, 5.0-V in-system |