EPM9560RI208-20 - 560-Macrocell CPLD, 12K Gates, 20ns | Intel (Altera)
MPN: EPM9560RI208-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.5 | $12,250.00 |
| 1,000 | $21.1 | $21,100.00 |
Drop-in alternatives for EPM9560RI208-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RI208-15N
β Drop-Inβ In Stock
$19.45 / Unit
View Datasheet βEPM9560RI208-15
β Drop-Inβ In Stock
$20.1 / Unit
View Datasheet βEPM9560RI208-10N
β Drop-Inβ In Stock
$61.75 / Unit
View Datasheet βEPM9560RI208-10
β Drop-Inβ In Stock
$67.8 / Unit
View Datasheet βEPM9560R1208-20
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$22.4 / Unit
View Datasheet βEPM9560RI208-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Usable Gates | 12,000 |
| Macro Cells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Propagation Delay (tPD) | 20 ns |
| Counter Frequency (fCNT) | 100 MHz |
| Supply Voltage (VCC) | 5.0 V |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| Package | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| Mounting Type | Surface Mount |
EPM9560RI208-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (LAB I/O bank) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | VCC β 5.0V supply |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 9 | TMS β JTAG Test Mode Select |
| Pin 10 | TCK β JTAG Test Clock |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | VCC β 5.0V supply |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-20 is suitable for 6 applications: Industrial Control and Factory Automation, Telecommunications Line Cards and Bus Bridging, Automotive Body Electronics and ECU Glue Logic, Legacy PCI/ISA Bus Bridges and Memory Interfacing, Networking Routers, Switches and Backplane Glue, Military and Aerospace Control Systems.
Industrial Control and Factory Automation
The EPM9560RI208-20 fits industrial control and factory automation designs because its 560 macrocells and 212 user I/O pins comfortably handle large state machines, address decoding, and bus arbitration between microcontrollers, motor drivers, sensors, and HMI peripherals. The 20 ns pin-to-pin delay provides 50 MHz+ operation, and CMOS EEPROM technology delivers zero-power standby - critical for always-on industrial PLCs and discrete I/O modules. The integrated IEEE 1149.1 JTAG interface enables in-field firmware updates without removing the module from service.
Recommended
Telecommunications Line Cards and Bus Bridging
The EPM9560RI208-20 is well suited for telecommunications line cards, especially legacy T1/E1 and ATM/SONET backplane interfaces where it performs glue logic between framers, SERDES devices, network processors, and TDM buses. The 100 MHz counter frequency supports 8 kHz framing and clock-recovery dividers, while the 20 ns propagation delay meets setup/hold margins on 33 MHz PCI-style buses. EEPROM-based ISP via JTAG allows field upgrades of protocol mappings without removing line cards.
Recommended
Automotive Body Electronics and ECU Glue Logic
The EPM9560RI208-20 suits automotive body ECUs, gateway modules, and instrument-cluster designs that need predictable timing for sensor fusion, CAN/LIN arbitration, and PWM fan/lighting control. The 560-macrocell density comfortably absorbs multiple state machines (door locks, lighting sequencing, wiper control), while 5.0-V tolerant I/O interfaces directly to legacy automotive peripherals. The CMOS EEPROM process ensures instant-on at vehicle power-up with no firmware load delay.
Recommended
Legacy PCI/ISA Bus Bridges and Memory Interfacing
The EPM9560RI208-20 excels at legacy PCI/ISA bus bridges and DRAM interfacing where deterministic timing closure matters more than raw logic density. The fixed PIA routing delay simplifies static timing analysis - critical for bus arbitration cycles, address decoding, and wait-state generation. The 212 user I/O pins allow a single CPLD to replace multiple discrete 74-series decoder/driver packages, reducing PCB area and BOM cost in retrocomputing and industrial-PC designs.
Recommended
Networking Routers, Switches and Backplane Glue
The EPM9560RI208-20 is appropriate for legacy router/switch backplane glue logic - link-status aggregation, LED driving, PHY interface adaptation, and power-sequencing control across multi-board systems. The 20 ns tPD comfortably handles 25 MHz and 50 MHz MDIO/MDC and parallel management bus rates, while EEPROM non-volatility eliminates in-system boot delays. JTAG ISP simplifies manufacturing test of complex backplane assemblies.
Recommended
Military and Aerospace Control Systems
The EPM9560RI208-20 remains specified in long-lifecycle military and aerospace programs because of its mature MAX 9000 architecture, EEPROM non-volatility (instant-on at -55C cold start), and tolerance of 5V supply transients common in 28V avionics buses with MIL-STD-704 compliance. The 560-macrocell density handles MIL-STD-1553 bus monitors, navigation display controllers, and redundant signal-arbitration paths. JTAG ISP supports depot-level firmware updates in the field.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-15N | EPM9560RI208-15 | EPM9560RI208-10N | EPM9560RI208-10 | EPM9560R1208-20 |
|---|---|---|---|---|---|---|
| Package | 208-pin RQFP (28x28 mm) | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns (-25%) | 15 ns (-25%) | 10 ns (-50%) | 10 ns (-50%) | 20 ns (identical) |
| Counter Frequency | 100 MHz | 100 MHz (identical) | 100 MHz (identical) | 125 MHz (+25%) | 125 MHz (+25%) | 100 MHz (identical) |
| Macro Cells | 560 | 560 (identical) | 560 (identical) | 560 (identical) | 560 (identical) | 560 (identical) |
| Usable Gates | 12,000 | 12,000 (identical) | 12,000 (identical) | 12,000 (identical) | 12,000 (identical) | 12,000 (identical) |
| Logic Array Blocks | 16 | 16 (identical) | 16 (identical) | 16 (identical) | 16 (identical) | 16 (identical) |
| Supply Voltage | 5.0 V | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) | 5.0 V (identical) |
| Lead-Free Finish | [DATA_NEEDED] | Yes (N suffix) | No (standard) | Yes (N suffix) | No (standard) | [DATA_NEEDED] |
Key Differentiators
- Highest logic density in MAX 9000 family (vs EPM9320RI208-20)
- Most cost-effective speed grade for timing-relaxed designs (vs EPM9560RI208-10)
- Zero-power standby via EEPROM technology (vs SRAM-based FPGA equivalents)
Design Notes
Place 0.1 uF and 10 uF decoupling capacitors adjacent to every VCC/GND pair of the EPM9560RI208-20. The 208-pin RQFP exposes VCC pins on multiple sides (typically pins 3, 15, ...); each must be individually decoupled to prevent simultaneous-switching-noise (SSN) from coupling into JTAG/programming pins during ISP operations. Keep the JTAG chain (TDI/TMS/TCK/TDO) trace lengths matched within 50 mils to preserve signal integrity.
Although the EPM9560RI208-20 is a 5.0-V device, ensure no I/O pin is driven above VCCIO during in-system programming. The IEEE 1149.1 JTAG controller can source 5V signals back into I/O banks if upstream drivers are not Hi-Z during programming - this can latch-up the EEPROM cells. Add series resistors (100 ohm) on TDI/TMS/TCK if driving from long cables.
When porting a MAX+PLUS II or Quartus design from EPM9560RI208-20 to a -15 or -10 speed grade, the same bitstream is fully forward-compatible (because the silicon die is identical), but timing closure becomes tighter. Always re-run static timing analysis after speed-grade substitution to confirm hold-time margins across all 16 LABs. The PIA routing delay is fixed, so the -20 part cannot be slowed down by software.
Compliance Information
RoHS and lead-free status were not in the verified web data; the EPM9560RI208-20 base part number is from the original 5V MAX 9000 family (mid-1990s era), so the standard (non-N-suffix) version is likely SnPb-finish, while the EPM9560RI208-15N / -10N variants are lead-free. AEC-Q100 is not applicable to commercial-grade Altera CPLDs.
