EPM9560RI208-20N vs EPM9560RI208-10N Comparison
Detailed side-by-side comparison of EPM9560RI208-20N by Intel and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-20N | EPM9560RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | 10 ns (speed grade -10) |
| Counter Speed | 100 MHz | — |
| Supply Voltage | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Package | 208-pin RQFP | 208-pin RQFP (PQFP) |
| Mounting Type | Surface Mount | — |
| Operating Temperature | Industrial (-40C to +85C) | -40C to +85C (Industrial grade, "RI" suffix) |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink) |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| User I/Os | — | 212 |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| MSL Level | — | 3 (168 Hours) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |