EPM9560RI208-10N - MAX 9000 CPLD, 12K Gates, 208-Pin RQFP
MPN: EPM9560RI208-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85.5 | $855.00 |
| 100 | $76 | $7,600.00 |
| 500 | $68.4 | $34,200.00 |
| 1,000 | $61.75 | $61,750.00 |
Drop-in alternatives for EPM9560RI208-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RI208-20N
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View Datasheet βEPM9560RI208-10
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View Datasheet βEPM9560ARI208-10N
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View Datasheet βEPM9560RC208-20
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View Datasheet βEPM9320RI208-20N
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View Datasheet βEPM9560RI208-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Usable Gates | 12,000 |
| Macro Cells | 560 |
| Register Bits | 12,160 |
| User I/Os | 212 |
| Pin-to-Pin Delay | 10 ns (speed grade -10) |
| Maximum Frequency | 100 MHz to 125 MHz |
| Supply Voltage | 5 V |
| Package | 208-pin RQFP (PQFP) |
| Operating Temperature | -40C to +85C (Industrial grade, "RI" suffix) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) |
| MSL Level | 3 (168 Hours) |
| RoHS Status | ROHS3 Compliant (per fpgalink) |
| Configuration Memory | On-chip EEPROM (non-volatile) |
EPM9560RI208-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (bidirectional) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | VCC β 5V supply voltage |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | TDI β JTAG Test Data In |
| Pin 14 | TMS β JTAG Test Mode Select |
| Pin 15 | TCK β JTAG Test Clock |
| Pin 16 | TDO β JTAG Test Data Out |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | VCC β 5V supply voltage |
| Pin 20 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-10N is suitable for 7 applications: 32-bit PCI Bus Interface Glue Logic, Address Decoding in Embedded Processor Systems, Bus Isolation and Multiplexing, State-Machine Controllers for Industrial Automation, Glue Logic in Mixed-Voltage Designs, Test and Measurement Equipment Front-End, Telecommunications Backplane Bridging.
32-bit PCI Bus Interface Glue Logic
The EPM9560RI208-10N's 212 user I/Os and 10 ns pin-to-pin delay make it well-suited for 32-bit PCI bus interface glue logic, where address decoding, command signal generation, and bus arbitration must complete within tight timing budgets. PCI at 33 MHz requires signals to settle within roughly 10 ns, matching the -10 speed grade's 10 ns delay specification. The device's 560 macro cells handle multiple address decode windows, parity generation, and interrupt steering simultaneously, and the non-volatile EEPROM configuration means the board powers up with valid logic state without a boot PROM.
Recommended
Address Decoding in Embedded Processor Systems
The EPM9560RI208-10N is commonly used as the central address decoder in embedded processor systems (e.g., 68000, x86, PowerPC), where it generates chip-select signals for memory banks, peripherals, and I/O devices from the CPU's address bus. Its 560 macro cells support multiple overlapping decode windows, and the 10 ns pin-to-pin response ensures chip-selects are valid before the peripheral's setup-time window closes. The non-volatile EEPROM configuration means the decoder is ready at power-on, and the JTAG interface allows field updates if the memory map is revised.
Recommended
Bus Isolation and Multiplexing
In mixed-processor systems with multiple bus masters (e.g., a DSP and a host processor sharing memory), the EPM9560RI208-10N isolates and multiplexes bus signals while maintaining deterministic timing. Its 212 user I/Os accommodate wide data buses (32-bit or 64-bit) plus address, control, and arbitration signals, and the 10 ns speed grade handles arbitration switching without violating peripheral timing. The deterministic interconnect delay (no routing-dependent skew, unlike FPGAs) makes it preferable for bus multiplexing where timing margins are tight and predictable.
Recommended
State-Machine Controllers for Industrial Automation
The EPM9560RI208-10N's industrial -40C to +85C operating range makes it suitable for state-machine controllers in industrial automation, including PLC I/O expansion modules, motor-control sequencers, and safety interlock logic. Its non-volatile configuration retains state-machine definitions across power cycles, eliminating the need for boot PROMs in harsh environments. The 560 macro cells implement complex multi-state machines (e.g., 16-state sequential controllers) with combinational output logic, and the JTAG interface allows in-field firmware updates for production-line flexibility.
Recommended
Glue Logic in Mixed-Voltage Designs
In designs that bridge 3.3V and 5V logic (common in legacy system upgrades), the EPM9560RI208-10N's 5V tolerant I/Os and 5V core supply provide the interface logic without external level shifters. The device's 212 user I/Os accommodate multiple voltage domains, and the 10 ns delay ensures signal integrity across voltage boundaries. This application is common in telecom backplane designs where legacy 5V peripherals must interface with newer 3.3V ASICs, and the CPLD's deterministic timing simplifies the timing closure process.
Recommended
Test and Measurement Equipment Front-End
The EPM9560RI208-10N is used in test and measurement equipment (e.g., logic analyzers, protocol analyzers, ATE) for trigger generation, pattern matching, and timing control. Its 212 user I/Os accommodate wide parallel data buses, and the 10 ns pin-to-pin delay allows precise timing alignment between multiple trigger sources. The non-volatile configuration stores test patterns and trigger conditions, while the JTAG interface enables field reconfiguration for different DUT protocols. The industrial temperature range supports laboratory and production-floor environments.
Recommended
Telecommunications Backplane Bridging
The EPM9560RI208-10N's 212 I/Os and 10 ns delay make it valuable for telecommunications backplane bridging applications, including TDM bus multiplexing, HDLC channel aggregation, and clock distribution. The non-volatile EEPROM configuration means the bridge is operational immediately at power-on, critical for telecom systems requiring fast recovery after power interruptions. The 5V supply and industrial temperature range support outdoor cabinet deployments, and the JTAG interface allows service technicians to update configuration in the field.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-20N | EPM9560RI208-10 | EPM9560ARI208-10N | EPM9560RC208-20 | EPM9320RI208-20N |
|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 5,000 |
| Macro Cells | 560 | 560 | 560 | 560 | 560 | 320 |
| User I/Os | 212 | 212 | 212 | 212 | 212 | 168 |
| Pin-to-Pin Delay | 10 ns | 20 ns | 10 ns | 10 ns | 20 ns | 20 ns |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C | -40C to +85C | -40C to +85C | 0C to +70C (Commercial) | -40C to +85C |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 10 ns pin-to-pin delay enables 33 MHz PCI bus support (vs EPM9560RI208-20N)
- Industrial temperature range (-40C to +85C) (vs EPM9560RC208-20)
- 560 macro cells with 212 user I/Os for wide bus interfaces (vs EPM9320RI208-20N)
- Non-volatile EEPROM configuration - no boot PROM required (vs FPGA with SRAM configuration)
Design Notes
The EPM9560RI208-10N requires a well-regulated 5V supply because its CMOS EEPROM programming voltage and core logic both derive from VCC. Place a 0.1 uF ceramic decoupling capacitor adjacent to each VCC pin (typically 4-6 VCC pins on the 208-pin RQFP) and add a single 10 uF bulk capacitor near the package. Simultaneous-switching output currents can exceed 200 mA during bus transitions, so use wide power traces and a solid ground plane to minimize supply bounce. A 100 ohm series resistor on the 5V rail can help if the supply has excessive ringing.
Route the JTAG signals (TCK, TMS, TDI, TDO) as a daisy-chained bus with no stubs, keeping total chain length under 6 inches to avoid signal integrity issues. Place a 10 kohm pull-up resistor on TCK, TMS, and TDI, and ensure TDO has a 10 kohm pull-up if multiple devices share the JTAG chain. The 208-pin RQFP requires a 1.27 mm pitch footprint with thermal relief on all ground pads; use a 4-layer PCB with dedicated VCC and GND planes for best signal integrity on the 212 I/O pins.
The EPM9560RI208-10N dissipates approximately 1.5-2.5W at full I/O toggle rates (all 212 outputs switching at 25 MHz), which can raise the junction temperature 30-50C above ambient on a standard 4-layer PCB without thermal vias. Add thermal vias (9-12 vias per GND pad) under the exposed thermal pad if the package has one, or increase the copper pour around the package. For industrial applications at +85C ambient, derate the toggle rate by 30% or add forced-air cooling to stay within the 125C junction limit.
Do not confuse the EPM9560RI208-10N (industrial, 10 ns, lead-free N suffix) with the EPM9560RC208-10 (commercial, 10 ns, leaded) or EPM9560RI208-20N (industrial, 20 ns). Verify the part number suffix carefully when ordering, as the speed grade and temperature range differ. Also note that the MAX 9000 family is obsolete - new designs should use MAX II, MAX V, or MAX 10 CPLDs. When migrating, recognize that the JTAG programming algorithm differs between MAX 9000 and MAX II/V/10, requiring updated programming software (Quartus II 9.0 or earlier for MAX 9000).
Compliance Information
ROHS3 Compliant per fpgalink.com. Lead-free assembly indicated by the N suffix. Not AEC-Q100 qualified - the MAX 9000 family pre-dates automotive-specific qualification programs, but the industrial temperature range supports many automotive under-hood applications. Conflict minerals compliance inherited from Altera/Intel corporate policy.
