EPM9560TC208-20 vs EPM9560RI208-20W Comparison
Detailed side-by-side comparison of EPM9560TC208-20 by Altera and EPM9560RI208-20W by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560TC208-20 | EPM9560RI208-20W |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Device Family | MAX 9000 | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12000 | 12,000 |
| User I/O | 149 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | -20 |
| Package | TQFP-208 (TC208) | 208-pin RQFP (Power Quad Flat Pack) |
| Pin/Package Code | TC208 (JEDEC S-PQFP-G208) | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Third-generation Multiple Array MatriX (MAX) |
| Technology | CMOS EEPROM | — |
| Core Supply Voltage | 5 V | — |
| I/O Supply Voltage (MultiVolt) | 3.3 V or 5 V | — |
| In-System Programming | Yes (IEEE Std 1149.1 JTAG) | — |
| Flip-Flops | 772 | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial temperature grade] | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount | — |
| RoHS Status | unknown | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 LABs of 40 macrocells each |
| User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | — | CMOS EEPROM |