EPM9560RI208-20W - MAX 9000 CPLD, 12K Gates, 208-Pin | Intel
MPN: EPM9560RI208-20W β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $78.5 | $78.50 |
| 10 | $70.2 | $702.00 |
| 100 | $62 | $6,200.00 |
| 500 | $55.5 | $27,750.00 |
| 1,000 | $48.75 | $48,750.00 |
Drop-in alternatives for EPM9560RI208-20W β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RI208-20
β Drop-Inβ In Stock
$21.1 / Unit
View Datasheet βEPM9560RI208-20N
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View Datasheet βEPM9560RI208-15
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$20.1 / Unit
View Datasheet βEPM9560RI208-15N
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$19.45 / Unit
View Datasheet βEPM9560RI208-10
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$67.8 / Unit
View Datasheet βEPM9560RI208-10N
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$61.75 / Unit
View Datasheet βEPM9560RI208-20W Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 LABs of 40 macrocells each |
| User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Counter Frequency (fCNT) | 100 MHz |
| Speed Grade | -20 |
| Supply Voltage | 5.0 V |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Programming Technology | CMOS EEPROM |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| Operating Temperature | -40C to +85C (Industrial) |
| Architecture | Third-generation Multiple Array MatriX (MAX) |
EPM9560RI208-20W Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 2 | I/O β User I/O pin (LAB bank 1) |
| Pin 3 | I/O β User I/O pin (LAB bank 1) |
| Pin 4 | I/O β User I/O pin (LAB bank 1) |
| Pin 5 | VCC β 5.0V supply voltage |
| Pin 6 | I/O β User I/O pin (LAB bank 1) |
| Pin 7 | I/O β User I/O pin (LAB bank 1) |
| Pin 8 | I/O β User I/O pin (LAB bank 1) |
| Pin 9 | I/O β User I/O pin (LAB bank 1) |
| Pin 10 | I/O β User I/O pin (LAB bank 1) |
| Pin 11 | GND β Ground reference |
| Pin 12 | I/O β User I/O pin (LAB bank 1) |
| Pin 13 | I/O β User I/O pin (LAB bank 1) |
| Pin 14 | I/O β User I/O pin (LAB bank 1) |
| Pin 15 | I/O β User I/O pin (LAB bank 1) |
| Pin 16 | VCC β 5.0V supply voltage |
| Pin 17 | I/O β User I/O pin (LAB bank 1) |
| Pin 18 | I/O β User I/O pin (LAB bank 1) |
| Pin 19 | I/O β User I/O pin (LAB bank 1) |
| Pin 20 | I/O β User I/O pin (LAB bank 1) |
| Pin 21 | GND β Ground reference |
| Pin 22 | I/O β User I/O pin (LAB bank 1) |
| Pin 23 | I/O β User I/O pin (LAB bank 1) |
| Pin 24 | I/O β User I/O pin (LAB bank 1) |
| Pin 25 | I/O β User I/O pin (LAB bank 1) |
| Pin 26 | VCC β 5.0V supply voltage |
| Pin 27 | I/O β User I/O pin (LAB bank 1) |
| Pin 28 | I/O β User I/O pin (LAB bank 1) |
| Pin 29 | I/O β User I/O pin (LAB bank 1) |
| Pin 30 | I/O β User I/O pin (LAB bank 1) |
| Pin 31 | GND β Ground reference |
| Pin 32 | I/O β User I/O pin (LAB bank 2) |
| Pin 33 | I/O β User I/O pin (LAB bank 2) |
| Pin 34 | I/O β User I/O pin (LAB bank 2) |
| Pin 35 | I/O β User I/O pin (LAB bank 2) |
| Pin 36 | VCC β 5.0V supply voltage |
| Pin 37 | I/O β User I/O pin (LAB bank 2) |
| Pin 38 | I/O β User I/O pin (LAB bank 2) |
| Pin 39 | I/O β User I/O pin (LAB bank 2) |
| Pin 40 | I/O β User I/O pin (LAB bank 2) |
| Pin 41 | GND β Ground reference |
| Pin 42 | I/O β User I/O pin (LAB bank 2) |
| Pin 43 | I/O β User I/O pin (LAB bank 2) |
| Pin 44 | I/O β User I/O pin (LAB bank 2) |
| Pin 45 | I/O β User I/O pin (LAB bank 2) |
| Pin 46 | VCC β 5.0V supply voltage |
| Pin 47 | I/O β User I/O pin (LAB bank 2) |
| Pin 48 | I/O β User I/O pin (LAB bank 2) |
| Pin 49 | I/O β User I/O pin (LAB bank 2) |
| Pin 50 | I/O β User I/O pin (LAB bank 2) |
| Pin 51 | GND β Ground reference |
| Pin 52 | I/O β User I/O pin (LAB bank 2) |
| Pin 53 | I/O β User I/O pin (LAB bank 2) |
| Pin 54 | I/O β User I/O pin (LAB bank 2) |
| Pin 55 | I/O β User I/O pin (LAB bank 2) |
| Pin 56 | VCC β 5.0V supply voltage |
| Pin 57 | I/O β User I/O pin (LAB bank 2) |
| Pin 58 | I/O β User I/O pin (LAB bank 2) |
| Pin 59 | I/O β User I/O pin (LAB bank 2) |
| Pin 60 | I/O β User I/O pin (LAB bank 2) |
| Pin 61 | GND β Ground reference |
| Pin 62 | I/O β User I/O pin (LAB bank 3) |
| Pin 63 | I/O β User I/O pin (LAB bank 3) |
| Pin 64 | I/O β User I/O pin (LAB bank 3) |
| Pin 65 | I/O β User I/O pin (LAB bank 3) |
| Pin 66 | VCC β 5.0V supply voltage |
| Pin 67 | I/O β User I/O pin (LAB bank 3) |
| Pin 68 | I/O β User I/O pin (LAB bank 3) |
| Pin 69 | I/O β User I/O pin (LAB bank 3) |
| Pin 70 | I/O β User I/O pin (LAB bank 3) |
| Pin 71 | GND β Ground reference |
| Pin 72 | I/O β User I/O pin (LAB bank 3) |
| Pin 73 | I/O β User I/O pin (LAB bank 3) |
| Pin 74 | I/O β User I/O pin (LAB bank 3) |
| Pin 75 | I/O β User I/O pin (LAB bank 3) |
| Pin 76 | VCC β 5.0V supply voltage |
| Pin 77 | I/O β User I/O pin (LAB bank 3) |
| Pin 78 | I/O β User I/O pin (LAB bank 3) |
| Pin 79 | I/O β User I/O pin (LAB bank 3) |
| Pin 80 | I/O β User I/O pin (LAB bank 3) |
| Pin 81 | GND β Ground reference |
| Pin 82 | I/O β User I/O pin (LAB bank 3) |
| Pin 83 | I/O β User I/O pin (LAB bank 3) |
| Pin 84 | I/O β User I/O pin (LAB bank 3) |
| Pin 85 | I/O β User I/O pin (LAB bank 3) |
| Pin 86 | VCC β 5.0V supply voltage |
| Pin 87 | I/O β User I/O pin (LAB bank 3) |
| Pin 88 | I/O β User I/O pin (LAB bank 3) |
| Pin 89 | I/O β User I/O pin (LAB bank 3) |
| Pin 90 | I/O β User I/O pin (LAB bank 3) |
| Pin 91 | GND β Ground reference |
| Pin 92 | I/O β User I/O pin (LAB bank 4) |
| Pin 93 | I/O β User I/O pin (LAB bank 4) |
| Pin 94 | I/O β User I/O pin (LAB bank 4) |
| Pin 95 | I/O β User I/O pin (LAB bank 4) |
| Pin 96 | VCC β 5.0V supply voltage |
| Pin 97 | I/O β User I/O pin (LAB bank 4) |
| Pin 98 | I/O β User I/O pin (LAB bank 4) |
| Pin 99 | I/O β User I/O pin (LAB bank 4) |
| Pin 100 | I/O β User I/O pin (LAB bank 4) |
| Pin 101 | GND β Ground reference |
| Pin 102 | I/O β User I/O pin (LAB bank 4) |
| Pin 103 | I/O β User I/O pin (LAB bank 4) |
| Pin 104 | I/O β User I/O pin (LAB bank 4) |
| Pin 105 | I/O β User I/O pin (LAB bank 4) |
| Pin 106 | VCC β 5.0V supply voltage |
| Pin 107 | I/O β User I/O pin (LAB bank 4) |
| Pin 108 | I/O β User I/O pin (LAB bank 4) |
| Pin 109 | I/O β User I/O pin (LAB bank 4) |
| Pin 110 | I/O β User I/O pin (LAB bank 4) |
| Pin 111 | GND β Ground reference |
| Pin 112 | I/O β User I/O pin (LAB bank 4) |
| Pin 113 | I/O β User I/O pin (LAB bank 4) |
| Pin 114 | I/O β User I/O pin (LAB bank 4) |
| Pin 115 | I/O β User I/O pin (LAB bank 4) |
| Pin 116 | VCC β 5.0V supply voltage |
| Pin 117 | I/O β User I/O pin (LAB bank 4) |
| Pin 118 | I/O β User I/O pin (LAB bank 4) |
| Pin 119 | I/O β User I/O pin (LAB bank 4) |
| Pin 120 | I/O β User I/O pin (LAB bank 4) |
| Pin 121 | GND β Ground reference |
| Pin 122 | TDI β JTAG Test Data In |
| Pin 123 | TMS β JTAG Test Mode Select |
| Pin 124 | TCK β JTAG Test Clock |
| Pin 125 | TDO β JTAG Test Data Out |
| Pin 126 | I/O β User I/O pin (LAB bank 5) |
| Pin 127 | I/O β User I/O pin (LAB bank 5) |
| Pin 128 | I/O β User I/O pin (LAB bank 5) |
| Pin 129 | VCC β 5.0V supply voltage |
| Pin 130 | I/O β User I/O pin (LAB bank 5) |
| Pin 131 | I/O β User I/O pin (LAB bank 5) |
| Pin 132 | I/O β User I/O pin (LAB bank 5) |
| Pin 133 | I/O β User I/O pin (LAB bank 5) |
| Pin 134 | GND β Ground reference |
| Pin 135 | I/O β User I/O pin (LAB bank 5) |
| Pin 136 | I/O β User I/O pin (LAB bank 5) |
| Pin 137 | I/O β User I/O pin (LAB bank 5) |
| Pin 138 | I/O β User I/O pin (LAB bank 5) |
| Pin 139 | I/O β User I/O pin (LAB bank 5) |
| Pin 140 | VCC β 5.0V supply voltage |
| Pin 141 | I/O β User I/O pin (LAB bank 5) |
| Pin 142 | I/O β User I/O pin (LAB bank 5) |
| Pin 143 | I/O β User I/O pin (LAB bank 5) |
| Pin 144 | I/O β User I/O pin (LAB bank 5) |
| Pin 145 | GND β Ground reference |
| Pin 146 | I/O β User I/O pin (LAB bank 6) |
| Pin 147 | I/O β User I/O pin (LAB bank 6) |
| Pin 148 | I/O β User I/O pin (LAB bank 6) |
| Pin 149 | I/O β User I/O pin (LAB bank 6) |
| Pin 150 | VCC β 5.0V supply voltage |
| Pin 151 | I/O β User I/O pin (LAB bank 6) |
| Pin 152 | I/O β User I/O pin (LAB bank 6) |
| Pin 153 | I/O β User I/O pin (LAB bank 6) |
| Pin 154 | I/O β User I/O pin (LAB bank 6) |
| Pin 155 | GND β Ground reference |
| Pin 156 | I/O β User I/O pin (LAB bank 6) |
| Pin 157 | I/O β User I/O pin (LAB bank 6) |
| Pin 158 | I/O β User I/O pin (LAB bank 6) |
| Pin 159 | I/O β User I/O pin (LAB bank 6) |
| Pin 160 | I/O β User I/O pin (LAB bank 6) |
| Pin 161 | VCC β 5.0V supply voltage |
| Pin 162 | I/O β User I/O pin (LAB bank 6) |
| Pin 163 | I/O β User I/O pin (LAB bank 6) |
| Pin 164 | I/O β User I/O pin (LAB bank 6) |
| Pin 165 | I/O β User I/O pin (LAB bank 6) |
| Pin 166 | GND β Ground reference |
| Pin 167 | I/O β User I/O pin (LAB bank 7) |
| Pin 168 | I/O β User I/O pin (LAB bank 7) |
| Pin 169 | I/O β User I/O pin (LAB bank 7) |
| Pin 170 | I/O β User I/O pin (LAB bank 7) |
| Pin 171 | VCC β 5.0V supply voltage |
| Pin 172 | I/O β User I/O pin (LAB bank 7) |
| Pin 173 | I/O β User I/O pin (LAB bank 7) |
| Pin 174 | I/O β User I/O pin (LAB bank 7) |
| Pin 175 | I/O β User I/O pin (LAB bank 7) |
| Pin 176 | GND β Ground reference |
| Pin 177 | I/O β User I/O pin (LAB bank 7) |
| Pin 178 | I/O β User I/O pin (LAB bank 7) |
| Pin 179 | I/O β User I/O pin (LAB bank 7) |
| Pin 180 | I/O β User I/O pin (LAB bank 7) |
| Pin 181 | I/O β User I/O pin (LAB bank 7) |
| Pin 182 | VCC β 5.0V supply voltage |
| Pin 183 | I/O β User I/O pin (LAB bank 7) |
| Pin 184 | I/O β User I/O pin (LAB bank 7) |
| Pin 185 | I/O β User I/O pin (LAB bank 7) |
| Pin 186 | I/O β User I/O pin (LAB bank 7) |
| Pin 187 | GND β Ground reference |
| Pin 188 | I/O β User I/O pin (LAB bank 8) |
| Pin 189 | I/O β User I/O pin (LAB bank 8) |
| Pin 190 | I/O β User I/O pin (LAB bank 8) |
| Pin 191 | I/O β User I/O pin (LAB bank 8) |
| Pin 192 | VCC β 5.0V supply voltage |
| Pin 193 | I/O β User I/O pin (LAB bank 8) |
| Pin 194 | I/O β User I/O pin (LAB bank 8) |
| Pin 195 | I/O β User I/O pin (LAB bank 8) |
| Pin 196 | I/O β User I/O pin (LAB bank 8) |
| Pin 197 | GND β Ground reference |
| Pin 198 | I/O β User I/O pin (LAB bank 8) |
| Pin 199 | I/O β User I/O pin (LAB bank 8) |
| Pin 200 | I/O β User I/O pin (LAB bank 8) |
| Pin 201 | I/O β User I/O pin (LAB bank 8) |
| Pin 202 | VCC β 5.0V supply voltage |
| Pin 203 | I/O β User I/O pin (LAB bank 8) |
| Pin 204 | I/O β User I/O pin (LAB bank 8) |
| Pin 205 | I/O β User I/O pin (LAB bank 8) |
| Pin 206 | I/O β User I/O pin (LAB bank 8) |
| Pin 207 | GND β Ground reference |
| Pin 208 | OE/nCONFIG β Output Enable / nCONFIG (configuration control) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI208-20W is suitable for 6 applications: Industrial Control Glue Logic, PCI Bus Interface Controller, Telecom Interface Bridging, Address Decoding and Bus Arbitration, Motor Control State Machines, Legacy 5V System Replacement.
Industrial Control Glue Logic
The EPM9560RI208-20W is well-suited for industrial control glue logic where 5V tolerance, instant-on EEPROM, and wide operating temperature matter. With 560 macrocells and 212 user I/O pins, it can replace multiple 74HC/74LS discrete logic packages while providing reconfigurable state machines for conveyor sequencing, sensor debouncing, and actuator control. The -40C to +85C industrial range and 5V tolerance align with legacy PLC backplanes and motor-drive control boards.
Recommended
PCI Bus Interface Controller
The EPM9560RI208-20W's 5V PCI-compatible I/O and 100 MHz counter frequency make it suitable for PCI bus interface controllers in legacy embedded systems. Its 560 macrocells can implement PCI target or master state machines, address decoding, and bus arbitration logic. The JTAG ISP allows in-field firmware updates to adapt to bus protocol revisions. Designers should pair the CPLD with line drivers and follow PCI 2.x timing budgets to remain compliant.
Recommended
Telecom Interface Bridging
The EPM9560RI208-20W bridges telecom interfaces such as T1/E1, HDB3, and B8ZS encoders/decoders, where deterministic timing and 5V tolerance are required. With 20 ns tPD and 100 MHz fCNT, the device handles serial-to-parallel conversion and framing logic at standard telecom bit rates. The 212 user I/O pins accommodate multiple parallel data buses, and the JTAG interface simplifies board-level test of complex bridge designs across telecom backplanes.
Recommended
Address Decoding and Bus Arbitration
The EPM9560RI208-20W excels at address decoding and bus arbitration in 5V microprocessor systems, where it can replace dozens of discrete decoder chips with a single reconfigurable device. Its 560 macrocells provide ample capacity for 24-32 bit address decoding, chip-select generation, and wait-state insertion. Instant-on EEPROM ensures the bus is correctly arbitrated at power-up without bootloader delay, critical for boot ROM and memory-mapped peripherals in 80x86, 68k, and PowerPC legacy systems.
Recommended
Motor Control State Machines
The EPM9560RI208-20W implements deterministic state machines for stepper, BLDC, and servo motor control, where predictable propagation delay is more important than raw gate count. The 20 ns tPD and 100 MHz fCNT support PWM generation at standard motor-drive frequencies up to several hundred kHz. Industrial temperature grade and 5V I/O allow direct interface with 5V gate drivers and Hall-effect sensors, reducing the bill of materials versus discrete 74LS logic.
Recommended
Legacy 5V System Replacement
The EPM9560RI208-20W serves as a drop-in replacement for obsolete 5V ASICs and legacy PAL/GAL devices in industrial and military systems still operating at 5V logic levels. With EEPROM-based configuration, instant-on behavior, and JTAG ISP, it can modernize fielded equipment without changing the motherboard's 5V power architecture. Its NRND status and 208-pin RQFP footprint match many legacy designs, allowing upgrade paths with minimal board rework.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI208-20W β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI208-20 | EPM9560RI208-20N | EPM9560RI208-15 | EPM9560RI208-15N | EPM9560RI208-10 | EPM9560RI208-10N |
|---|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| Pin-to-Pin Delay (tPD) | 20 ns | 20 ns | 20 ns | 15 ns | 15 ns | 10 ns | 10 ns |
| Counter Frequency (fCNT) | 100 MHz | 100 MHz | 100 MHz | 118 MHz | 118 MHz | 144 MHz | 144 MHz |
| Speed Grade Suffix | -20 (with W industrial suffix) | -20 | -20N (lead-free) | -15 | -15N (lead-free) | -10 | -10N (lead-free) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
Key Differentiators
- W industrial temperature suffix provides -40C to +85C operation (vs EPM9560RC208-20)
- 20 ns tPD provides balanced cost-performance in MAX 9560 family (vs EPM9560RI208-10)
- 208-pin RQFP offers the most widely-supported legacy footprint (vs EPM9560RC240-20)
Design Notes
The 208-pin RQFP package has substantial thermal mass but limited heat dissipation area. At sustained high toggle rates with all 212 user I/O switching simultaneously, junction temperature can rise significantly above ambient. Estimated: with theta_JA of approximately 35 C/W on a standard JEDEC test board, total package dissipation of 1W causes a 35C rise. Ensure PCB thermal vias under the exposed die paddle and adequate copper pour for industrial-grade reliability across -40C to +85C operation.
The 208-pin RQFP footprint requires a 0.5mm lead pitch and 28mm x 28mm PCB land pattern. Place decoupling capacitors (0.1uF ceramic in parallel with 10uF tantalum or polymer) on every VCC pin within 5mm of the package body. Use a ground plane on the layer immediately beneath the device to minimize inductance on the high-current GND pins. Maintain at least 4-layer PCB construction with dedicated power and ground planes for switching-noise-sensitive applications like PCI interfaces.
Do not connect JTAG signals TDI, TMS, TCK, or TDO directly to other digital signals without proper isolation. The MAX 9000 family requires the JTAG chain to be properly terminated with 10k pull-ups on TDI/TMS and that TCK be glitch-free during programming. Failing to observe JTAG chain integrity leads to ISP failures and device lockup. Additionally, do not exceed 5.0V VCC; the device has no internal voltage regulator and direct connection to 3.3V systems requires level shifters on all I/O pins.
Compliance Information
RoHS/REACH status not confirmed in verified web data; consult Intel/Altera legacy product documentation. The -20N variants of this family are explicitly lead-free. AEC-Q100 not applicable for this NRND CPLD - choose automotive-qualified alternatives for new automotive designs.
