EPM9560TC208-20 - MAX 9000 CPLD, 560 Macrocells, TQFP-208 | Altera
MPN: EPM9560TC208-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $85.5 | $855.00 |
| 100 | $76 | $7,600.00 |
| 500 | $68 | $34,000.00 |
| 1,000 | $60 | $60,000.00 |
Drop-in alternatives for EPM9560TC208-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC208-20
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View Datasheet →EPM9560RC208-20N
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View Datasheet →EPM9560RC208-20C
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View Datasheet →EPM9560RI208-20
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$21.1 / Unit
View Datasheet →EPM9560RI208-20N
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View Datasheet →EPM9560RI208-20W
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View Datasheet →EPM9560TC208-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Macrocells | 560 |
| Usable Gates | 12000 |
| User I/O | 149 |
| Propagation Delay (tPD) | 20 ns |
| Speed Grade | -20 |
| Package | TQFP-208 (TC208) |
| Pin/Package Code | TC208 (JEDEC S-PQFP-G208) |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Technology | CMOS EEPROM |
| Core Supply Voltage | 5 V |
| I/O Supply Voltage (MultiVolt) | 3.3 V or 5 V |
| In-System Programming | Yes (IEEE Std 1149.1 JTAG) |
| Flip-Flops | 772 |
| Mounting Type | Surface Mount |
| RoHS Status | unknown |
EPM9560TC208-20 tc208 (jedec s-pqfp-g208) Pin Configuration Guide
Complete pinout information for EPM9560TC208-20 (tc208 (jedec s-pqfp-g208) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560TC208-20.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560TC208-20 is suitable for 6 applications: Industrial Control Glue Logic, Telecom Bus Interfacing and Bridging, Microprocessor Address Decoding and Chip-Select Generation, PCI Bus Interface Bridging, Embedded State-Machine Controllers, Legacy Industrial Sustaining Engineering.
Industrial Control Glue Logic
The EPM9560TC208-20's 560 macrocells and 149 user I/O fit industrial control panels where distributed glue logic, address decoding, and bus steering must be consolidated onto a single non-volatile CPLD. With a 20 ns tPD it can replace multiple 22V10 or 16V8 PALs while freeing board area for sensor interfaces. The 5V core and MultiVolt I/O (3.3V/5V) interface directly to legacy 5V ASICs and 3.3V microcontrollers without level shifters. JTAG-ISP enables field firmware updates without removing the board from the control cabinet, critical for installed-base retrofits. The 12K usable gates comfortably hold PID loop glue, watchdog state machines, and safety interlocks. Designers should provision adequate bulk decoupling (10 uF + 100 nF) on each VCC pin group and route JTAG TMS/TCK/TDI/TDO as a protected chain.
Recommended
Telecom Bus Interfacing and Bridging
In telecom equipment the EPM9560TC208-20 bridges asynchronous backplane buses (such as legacy VME or proprietary point-to-point links) to host CPUs, with 149 I/O supporting wide parallel interfaces and 20 ns tPD matching common 25-50 MHz bus cycle budgets. MultiVolt I/O (3.3V/5V) lets a single CPLD connect 5V legacy ASICs to 3.3V processors, eliminating external transceivers. The 772 flip-flops hold bus-state registers, FIFOs, and protocol state machines in deterministic logic, which is preferable to microsecond-jitter software drivers for telecom timing. JTAG-ISP enables remote firmware updates through boundary-scan chains when physical access to the card is impossible. Place the EPM9560 adjacent to bus transceivers with matched-impedance trace lengths and guard the JTAG pins with ESD protection diodes.
Recommended
Microprocessor Address Decoding and Chip-Select Generation
With 12,000 usable gates and 560 macrocells, the EPM9560TC208-20 replaces several discrete address decoder PALs in a microprocessor subsystem, generating chip-selects for ROM, RAM, peripherals, and memory-mapped I/O. The 20 ns tPD ensures the chip-select arrives within the same clock cycle as the address, meeting 25-33 MHz CPU bus budgets without wait states. MultiVolt I/O lets a single CPLD interface to both 5V peripheral buses and 3.3V processor cores. JTAG-ISP enables late-stage memory-map changes during prototype bring-up without socketing the CPLD. Allocate one global clock input to the system clock, drive enables from dedicated input pins for clean timing analysis, and minimize combinatorial depth between address-input and chip-select-output macros.
Recommended
PCI Bus Interface Bridging
The EPM9560TC208-20 is well suited for legacy 5V PCI bus bridge designs: 149 user I/O accommodate the 32-bit multiplexed address/data bus plus command/byte-enable signals, while 20 ns tPD satisfies 33 MHz PCI timing budgets (the legacy -20 speed grade offers headroom for the 30 ns target). MultiVolt I/O lets the same CPLD interface to 5V PCI peripherals and 3.3V host ASICs simultaneously. The 12K usable gates implement target state machines, configuration-space registers, and parity logic in deterministic hardware. Engineers should use dedicated input pins for PCI clock and FRAME#, allocate macrocell flip-flops for registered output signals to meet PCI setup/hold requirements, and verify pinout against the PCI Local Bus Specification before board layout.
Recommended
Embedded State-Machine Controllers
The EPM9560TC208-20 implements deterministic state-machine controllers for embedded systems where microsecond latency and predictable behavior matter more than absolute logic density. With 560 macrocells and 772 flip-flops, designers can encode complex multi-state control loops, watchdogs, and safety interlocks in hardware-verified logic rather than interrupt-driven firmware. The 20 ns tPD suits 50 MHz internal state-machine clocks, and the JTAG-ISP port lets developers iterate state diagrams in-circuit during prototype bring-up. MultiVolt I/O interfaces to 5V sensor buses and 3.3V host MCUs without glue logic. For maximum deterministic behavior, register all state outputs and isolate asynchronous inputs with synchronizer macros at the chip boundary.
Recommended
Legacy Industrial Sustaining Engineering
The EPM9560TC208-20's primary modern role is sustaining engineering of long-lifecycle industrial equipment (medical instrumentation, factory automation controllers, military/aerospace subsystems) where redesign is prohibitively expensive and the board footprint is locked to TQFP-208. With 560 macrocells and identical MAX architecture as the original deployment, second-source parts in the same 208-pin footprint can drop into existing boards with no PCB rework. Authorized independent distributors stock factory-traceable parts for sustained support; engineers should require certificates of conformance and date-code verification on every shipment. For long-term roadmap planning, design houses should plan migration to MAX II EPM570F100C5N or MAX V 5M240ZT100, accepting that PCB redesign will be required.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560TC208-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-20 | EPM9560RC208-20N | EPM9560RC208-20C | EPM9560RI208-20 | EPM9560RI208-20N | EPM9560RI208-20W |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | TQFP-208 (TC208) | PQFP-208 (RC208) | PQFP-208 (RC208) | PQFP-208 (RC208) | 208-pin (RI208) | 208-pin (RI208) | 208-pin (RI208) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | ||
| Usable Gates | 12000 | 12000 | 12000 | 12000 | |||
| Propagation Delay (tPD) | 20 ns | 20 ns | 20 ns | 20 ns | |||
| User I/O | 149 | 149 | 149 | 149 | |||
| Speed Grade | -20 | -20 | -20 | -20 | |||
| In-System Programming | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | |||
| Core Voltage | 5 V | 5 V | 5 V | 5 V | |||
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Third-generation MAX architecture with 12,000 usable gates (vs EPM9480TC208-20)
- TQFP package with 0.5 mm pitch for high-density PCB layouts (vs EPM9560RC208-20 (PQFP-208))
- 149 user I/O for high-fan-out bus bridging (vs MAX V 5M240ZT100)
Design Notes
Place 100 nF ceramic decoupling capacitors within 3 mm of every VCC/IOVCC pin group on the TQFP-208 footprint, with one bulk 10 uF tantalum or ceramic capacitor near each VCC plane entry. The MAX 9000 family datasheet recommends one 0.1 uF cap per VCC pin and 1-2 bulk caps per supply rail. Proper decoupling prevents logic errors during simultaneous switching of multiple output banks, which is critical at the EPM9560's 149-I/O fan-out. Use a continuous ground plane under the device for low-impedance return paths.
Route JTAG signals TMS, TCK, TDI, TDO as a guarded chain with series 10-100 ohm damping resistors near the CPLD, keeping the chain away from fast-edge signals. Provide a JTAG header or test-pad cluster on the board for in-system programming. Tie unused I/O pins to defined logic levels (do not float) to reduce quiescent current and prevent oscillation. Use the MAX+PLUS II/Quartus fitter pinout report to verify reserved-pin assignments before PCB layout freeze.
Estimated: at 33 MHz PCI bus operation with the -20 speed grade, designers have approximately 30 ns of timing budget. The 20 ns tPD specification leaves only ~10 ns for output buffer delay and setup-time margin. Always use registered outputs for signals entering the PCI bus, and verify the worst-case pin-to-pin delay in the Quartus Timing Analyzer rather than relying on the family tPD headline number. Do not exceed 5V on any I/O pin (MultiVolt supports 3.3V/5V but not 2.5V or 1.8V); use external level shifters for lower-voltage interfaces.
Compliance Information
Compliance information not present in verified web data. The MAX 9000 family predates widespread RoHS adoption (2006) and many parts ship in non-RoHS finishes; lead-free variants carry the 'N' suffix (e.g. EPM9560RC208-20N). Confirm RoHS/lead-free status with the distributor's certificate of conformance when ordering for new designs.
