EPM9560WC208-15 vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-15 | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | — |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| Flip-Flops | 772 | 772 |
| User I/O Pins (max) | 149 | — |
| Maximum Clock Frequency | 117.6 MHz | 100 MHz |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | — |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (28x28 mm) |
| Terminal Pitch | 0.50 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| RoHS Status | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 (EPM9560) |
| Usable Gates | — | 12,000 |
| Logic Array Blocks | — | 35 |
| User I/O Pins | — | 153 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature | — | 0C to +70C (commercial) |
| I/O Standards | — | 5.0 V TTL/CMOS compatible |
| MSL Level | — | [DATA_NEEDED: MSL level] |