EPM9560RC208-20 - MAX 9000 CPLD 560 Macrocell 20ns | Intel
MPN: EPM9560RC208-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM9560RC208-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-15
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9560RC208-19
β Drop-Inβ In Stock
$16.2 / Unit
View Datasheet βEPM9560RC208-18
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View Datasheet βEPM9560RC208-17
β Drop-Inβ In Stock
$54.75 / Unit
View Datasheet βEPM9560RC208-16
β Drop-Inβ In Stock
$52.4 / Unit
View Datasheet βEPM9560RC208-15N
β Drop-Inβ In Stock
$19.85 / Unit
View Datasheet βEPM9560RC208-20 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 (EPM9560) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks | 35 |
| User I/O Pins | 153 |
| Pin-to-Pin Delay (tPD) | 20 ns |
| Maximum Clock Frequency | 100 MHz |
| Supply Voltage | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG |
| Package | 208-pin RQFP (28x28 mm) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| I/O Standards | 5.0 V TTL/CMOS compatible |
| Flip-Flops | 772 |
EPM9560RC208-20 Pin Configuration
| Pin 1 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 2 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 3 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 4 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 5 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 6 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 7 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 8 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 9 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 10 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 11 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 12 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 13 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 14 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 15 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 16 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 17 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 18 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 19 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 20 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 21 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 22 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 23 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 24 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 25 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 26 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 27 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 28 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 29 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 30 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 31 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 32 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 33 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 34 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 35 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 36 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 37 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 38 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 39 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 40 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 41 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 42 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 43 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 44 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 45 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 46 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 47 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 48 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 49 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 50 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 51 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 52 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 53 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 54 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 55 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 56 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 57 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 58 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 59 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 60 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 61 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 62 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 63 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 64 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 65 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 66 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 67 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 68 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 69 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 70 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 71 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 72 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 73 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 74 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 75 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 76 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 77 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 78 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 79 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 80 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 81 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 82 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 83 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 84 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 85 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 86 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 87 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 88 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 89 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 90 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 91 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 92 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 93 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 94 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 95 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 96 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 97 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 98 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 99 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 100 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 101 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 102 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 103 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 104 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 105 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 106 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 107 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 108 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 109 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 110 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 111 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 112 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 113 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 114 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 115 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 116 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 117 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 118 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 119 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 120 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 121 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 122 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 123 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 124 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 125 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 126 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 127 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 128 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 129 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 130 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 131 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 132 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 133 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 134 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 135 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 136 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 137 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 138 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 139 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 140 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 141 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 142 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 143 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 144 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 145 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 146 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 147 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 148 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 149 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 150 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 151 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 152 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 153 | I/O β User I/O pin (per MAX 9000 datasheet) |
| Pin 154 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 155 | GND β Ground (per MAX 9000 datasheet) |
| Pin 156 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 157 | GND β Ground (per MAX 9000 datasheet) |
| Pin 158 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 159 | GND β Ground (per MAX 9000 datasheet) |
| Pin 160 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 161 | GND β Ground (per MAX 9000 datasheet) |
| Pin 162 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 163 | GND β Ground (per MAX 9000 datasheet) |
| Pin 164 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 165 | GND β Ground (per MAX 9000 datasheet) |
| Pin 166 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 167 | GND β Ground (per MAX 9000 datasheet) |
| Pin 168 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 169 | GND β Ground (per MAX 9000 datasheet) |
| Pin 170 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 171 | GND β Ground (per MAX 9000 datasheet) |
| Pin 172 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 173 | GND β Ground (per MAX 9000 datasheet) |
| Pin 174 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 175 | GND β Ground (per MAX 9000 datasheet) |
| Pin 176 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 177 | GND β Ground (per MAX 9000 datasheet) |
| Pin 178 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 179 | GND β Ground (per MAX 9000 datasheet) |
| Pin 180 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 181 | GND β Ground (per MAX 9000 datasheet) |
| Pin 182 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 183 | GND β Ground (per MAX 9000 datasheet) |
| Pin 184 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 185 | GND β Ground (per MAX 9000 datasheet) |
| Pin 186 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 187 | GND β Ground (per MAX 9000 datasheet) |
| Pin 188 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 189 | GND β Ground (per MAX 9000 datasheet) |
| Pin 190 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 191 | GND β Ground (per MAX 9000 datasheet) |
| Pin 192 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 193 | GND β Ground (per MAX 9000 datasheet) |
| Pin 194 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 195 | GND β Ground (per MAX 9000 datasheet) |
| Pin 196 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 197 | GND β Ground (per MAX 9000 datasheet) |
| Pin 198 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 199 | GND β Ground (per MAX 9000 datasheet) |
| Pin 200 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 201 | GND β Ground (per MAX 9000 datasheet) |
| Pin 202 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 203 | GND β Ground (per MAX 9000 datasheet) |
| Pin 204 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
| Pin 205 | GND β Ground (per MAX 9000 datasheet) |
| Pin 206 | VCCINT β 5.0 V core power supply (per MAX 9000 datasheet) |
| Pin 207 | GND β Ground (per MAX 9000 datasheet) |
| Pin 208 | VCCIO β 5.0 V I/O power supply (per MAX 9000 datasheet) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-20 is suitable for 6 applications: Legacy 5V Microprocessor Glue Logic, PCI and ISA Bus Interface Bridging, Industrial Control State Machines, Discrete 74-Series Logic Replacement, Telecom Line Card Control Logic, Test and Measurement Instrumentation.
Legacy 5V Microprocessor Glue Logic
The EPM9560RC208-20 fits legacy 5.0 V microprocessor glue logic because its 153 user I/O pins and 5.0 V TTL/CMOS-compatible I/O interface directly with classic 8/16-bit MPU buses without level shifters. Its 560 macrocells and 12,000 gates absorb address decoding, wait-state generation, and chip-select logic that would otherwise require dozens of 74-series packages. The 20 ns pin-to-pin delay keeps combinational decode paths within a single bus cycle at 100 MHz system clocks. Because configuration is stored in non-volatile EEPROM, the device is live immediately at power-up, unlike SRAM-based FPGAs that need a boot configuration step. The trade-off is higher static power from the 5.0 V core compared with modern 1.8 V CPLDs.
Recommended
PCI and ISA Bus Interface Bridging
The EPM9560RC208-20 suits PCI and ISA bus bridging because its 153 I/O pins and 5.0 V signaling match the legacy 5 V PCI/ISA electrical environment, and its 560 macrocells implement target/slave state machines, address translation, and handshake logic in a single non-volatile device. The 20 ns pin-to-pin delay supports the 33 MHz PCI clock domain with margin, while the 100 MHz maximum clock rate covers faster local logic. EEPROM configuration means the bridge is active before the host CPU releases reset, avoiding the configuration latency of SRAM FPGAs. Designers should budget for the 5.0 V core power and confirm the RQFP thermal pad soldering for reliable operation.
Recommended
Industrial Control State Machines
The EPM9560RC208-20 is well suited to industrial control state machines because its 560 macrocells and 772 flip-flops implement complex sequential logic, while the non-volatile EEPROM configuration guarantees deterministic startup in factory environments where a configuration PROM failure would halt the line. The 5.0 V I/O interfaces directly with legacy PLC backplanes and 24 V opto-isolated input conditioning, and the 20 ns pin-to-pin delay provides predictable timing for interlock logic. The 208-pin RQFP package offers 153 I/O for multi-axis or multi-station control. The main trade-off is the obsolete lifecycle status, so spare-parts planning is essential for long-lived industrial equipment.
Recommended
Discrete 74-Series Logic Replacement
The EPM9560RC208-20 replaces banks of discrete 74-series logic because a single 208-pin RQFP consolidates 560 macrocells and 12,000 gates, shrinking board area and reducing component count versus dozens of SSI/MSI packages. The 5.0 V TTL/CMOS-compatible I/O preserves the original logic levels, so existing 5 V designs need no level translation, and the 20 ns pin-to-pin delay matches or exceeds typical 74F/74LS propagation delays. Non-volatile EEPROM configuration removes the need for external configuration memory. The trade-off is that the obsolete MAX 9000 family requires careful sourcing; for new designs, a modern CPLD is preferable.
Recommended
Telecom Line Card Control Logic
The EPM9560RC208-20 fits telecom line card control logic because its 153 I/O pins and 560 macrocells handle per-channel control, alarm monitoring, and bus arbitration across multiple line interfaces, while the 5.0 V I/O matches legacy telecom backplane signaling. The 20 ns pin-to-pin delay and 100 MHz maximum clock support the control-plane timing of classic SONET/SDH and T1/E1 line cards. Non-volatile EEPROM configuration ensures the card is operational immediately after hot-swap power-up, which is critical for central-office equipment. The obsolete lifecycle means these parts are now sourced from remaining stock, so qualification of alternate speed grades is advisable.
Recommended
Test and Measurement Instrumentation
The EPM9560RC208-20 suits test and measurement instrumentation because its 560 macrocells and 772 flip-flops implement trigger sequencers, pattern generators, and acquisition state machines, while the 20 ns pin-to-pin delay provides deterministic timing for time-critical measurement paths. The 5.0 V I/O interfaces directly with legacy instrument front-end logic and DAC/ADC control buses, and the non-volatile EEPROM configuration guarantees repeatable power-up behavior in benchtop equipment. The 208-pin RQFP provides 153 I/O for multi-channel instruments. Because the MAX 9000 family is obsolete, designers maintaining existing instruments should stock spare devices and validate faster speed grades as drop-in substitutes.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-15 | EPM9560RC208-19 | EPM9560RC208-18 | EPM9560RC208-17 | EPM9560RC208-16 | EPM9560RC208-15N |
|---|---|---|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Pin-to-Pin Delay (tPD) | 20 ns | 15 ns | 19 ns | 18 ns | 17 ns | 16 ns | 15 ns |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 153 | 153 | 153 | 153 | 153 | 153 | 153 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Lead-Free Finish | [DATA_NEEDED: lead-free finish] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | Yes (N suffix) |
Key Differentiators
- 20 ns speed grade balances timing margin and cost (vs EPM9560RC208-15)
- Non-volatile EEPROM configuration (vs EPM9560RC208-19)
- Lead-free option available via N-suffix variant (vs EPM9560RC208-15N)
Design Notes
Decouple every VCCINT and VCCIO pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus a bulk 10 uF capacitor per power rail. The MAX 9000 family operates from a 5.0 V supply with separate core and I/O rails; keep the core rail within the datasheet tolerance to avoid configuration retention issues. Estimated: at 100 MHz with typical toggle rates, dynamic current can reach several hundred milliamps, so size the regulator and copper for the worst-case load rather than the quiescent value.
The 208-pin RQFP requires careful land-pattern design: use the manufacturer-recommended footprint with a thermal/ground pad, and reflow-solder with a profile matched to the package's moisture sensitivity level. Route the JTAG signals (TCK, TMS, TDI, TDO) as short, controlled-impedance traces and keep them away from high-speed I/O to avoid programming failures. Provide a dedicated ground plane under the device to control return paths.
Do not assume the EPM9560RC208-20 is still in production: the MAX 9000 family is obsolete, so verify date codes and authenticity when sourcing from independent distributors. When substituting a faster speed grade such as the EPM9560RC208-15, re-run static timing analysis because the faster grade changes internal delays and may alter hold-time margins. Also confirm the JTAG chain order if multiple programmable devices share the scan chain.
Compliance Information
Compliance data for the EPM9560RC208-20 was not present in the verified web data; values are set to unknown rather than assumed. The N-suffix ordering code (e.g. EPM9560RC208-15N) indicates a lead-free finish, but the standard -20 part's finish is not confirmed.
