EPM9560WC208-20 vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208-20 by Altera and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete
Specification Comparison
| Parameter | EPM9560WC208-20 | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| User I/O Pins | 149 | 153 |
| Maximum Propagation Delay (tPD) | 23.6 ns | — |
| Package | PQFP-208 (RQFP/WQFP) | 208-pin RQFP (28x28 mm) |
| Process Technology | CMOS, EEPROM-based | — |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | — |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | — |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED] | — |
| Halogen Free | [DATA_NEEDED] | — |
| MSL Level | [DATA_NEEDED] | [DATA_NEEDED: MSL level] |
| Device Family | — | MAX 9000 (EPM9560) |
| Usable Gates | — | 12,000 |
| Logic Array Blocks | — | 35 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Clock Frequency | — | 100 MHz |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| I/O Standards | — | 5.0 V TTL/CMOS compatible |
| Flip-Flops | — | 772 |