EPM9560WC208-20 vs EPM9560WC208-15 Comparison
Detailed side-by-side comparison of EPM9560WC208-20 by Altera and EPM9560WC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208-20 - 560-Macrocell CPLD, 23.6ns, PQFP-208 | Intel/Altera
EPM9560WC208-20 Obsolete
Specification Comparison
| Parameter | EPM9560WC208-20 | EPM9560WC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (EPLD) | EE PLD (Electrically Erasable Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| User I/O Pins | 149 | — |
| Maximum Propagation Delay (tPD) | 23.6 ns | — |
| Package | PQFP-208 (RQFP/WQFP) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Process Technology | CMOS, EEPROM-based | — |
| Supply Voltage (VCCINT) | 5 V (typical, see datasheet) | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (multi-voltage I/O) | — |
| In-System Programmability | Yes, JTAG BST (IEEE 1149.1) | — |
| Pin/Package Suffix | W = power PQFP; -20 = 23.6 ns speed grade | — |
| Operating Temperature | Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] | RoHS3 Compliant (per third-party listings) |
| Lead-Free | [DATA_NEEDED] | — |
| Halogen Free | [DATA_NEEDED] | — |
| MSL Level | [DATA_NEEDED] | — |
| Technology | — | CMOS |
| Flip-Flops | — | 772 |
| User I/O Pins (max) | — | 149 |
| Maximum Clock Frequency | — | 117.6 MHz |
| Propagation Delay (tPD) | — | 16.6 ns |
| Speed Grade | — | -15 |
| Supply Voltage - I/O | — | 3.3 V or 5.0 V (configurable) |
| Terminal Pitch | — | 0.50 mm |
| Programming Interface | — | JTAG (IEEE 1149.1 boundary scan) |