EPM9560WC208-20 vs EPM9560WC208-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560WC208-20 sa pamamagitan ng Altera at EPM9560WC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560WC208-20 EPM9560WC208-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (EPLD) EE PLD (Electrically Erasable Programmable Logic Device)
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
User I/O Pins 149 —
Maximum Propagation Delay (tPD) 23.6 ns —
Packhaging PQFP-208 (RQFP/WQFP) 208-pin CQFP (Ceramic Quad Flat Pack)
Process Technology CMOS, EEPROM-based —
Supply Voltage (VCCINT) 5 V (typical, see datasheet) —
I/O Voltage (VCCIO) 3.3 V or 5 V (multi-voltage I/O) —
In-System Programmability Yes, JTAG BST (IEEE 1149.1) —
Pin/Package Suffix W = power PQFP; -20 = 23.6 ns speed grade —
Temperature na Operasyon Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] RoHS3 Compliant (per third-party listings)
Lead-Free [DATA_NEEDED] —
Wala sa Halogen [DATA_NEEDED] —
Level ng MSL [DATA_NEEDED] —
Technology — CMOS
Flip-Flops — 772
User I/O Pins (max) — 149
Maksimum na Taktiko ng Oras — 117.6 MHz
Propagation Delay (tPD) — 16.6 ns
Speed Grade — -15
Supply Voltage - I/O — 3.3 V or 5.0 V (configurable)
Terminal Pitch — 0.50 mm
Programming Interface — JTAG (IEEE 1149.1 boundary scan)

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