EPM9560WC208-20 vs EPM9560WC208-15C Comparison

Detailed side-by-side comparison of EPM9560WC208-20 by Altera and EPM9560WC208-15C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560WC208-20 EPM9560WC208-15C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $25.80 $178.00
Family MAX 9000 β€”
Device Type CPLD (EPLD) β€”
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
User I/O Pins 149 149
Maximum Propagation Delay (tPD) 23.6 ns β€”
Package PQFP-208 (RQFP/WQFP) CQFP-208 (Ceramic Quad Flat Pack)
Process Technology CMOS, EEPROM-based 0.35 Β΅m CMOS EEPROM
Supply Voltage (VCCINT) 5 V (typical, see datasheet) β€”
I/O Voltage (VCCIO) 3.3 V or 5 V (multi-voltage I/O) β€”
In-System Programmability Yes, JTAG BST (IEEE 1149.1) β€”
Pin/Package Suffix W = power PQFP; -20 = 23.6 ns speed grade β€”
Operating Temperature Commercial (0C to +70C) [DATA_NEEDED: exact temp grade] β€”
Mounting Type Surface Mount Surface Mount
RoHS Status Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc] ROHS3 Compliant
Lead-Free [DATA_NEEDED] β€”
Halogen-Free [DATA_NEEDED] β€”
MSL Level [DATA_NEEDED] β€”
Device Family β€” MAX 9000
Series β€” EPM9560
Flip-Flops β€” 772
Supply Voltage β€” 3.3 V or 5 V
Maximum Clock Frequency β€” 117.6 MHz
Pin-to-Pin Propagation Delay (tPD) β€” 16.6 ns
Terminal Pitch β€” 0.50 mm
Programming Interface β€” IEEE 1149.1 JTAG
Operating Temperature Grade β€” C (Commercial)
MultiVolt I/O β€” Yes (3.3 V / 5 V tolerant)
Moisture Sensitivity Level (MSL) β€” 3 (168 Hours)

Datasheets & Resources

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