EPM9560WC208-20C vs EPM9560RC208-20 Comparison
Detailed side-by-side comparison of EPM9560WC208-20C by Altera and EPM9560RC208-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560WC208-20C | EPM9560RC208-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 (EE PLD) | MAX 9000 (EPM9560) |
| Series | EPM9560 | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | — |
| User I/O Pins | 149 | 153 |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Clock Frequency | [DATA_NEEDED: fMAX value not in verified data] | 100 MHz |
| Process Technology | CMOS, Electrically Erasable | — |
| Supply Voltage | 3.3 V or 5 V (configurable I/O) | 5.0 V |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin RQFP (28x28 mm) |
| Pin Count | 208 | — |
| Programming Interface | JTAG BST (in-system programmable) | — |
| Operating Temperature Grade | Commercial (C suffix) | — |
| Mounting Type | Surface Mount (Ceramic QFP) | Surface Mount |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level | MSL 3 (168 Hours) | — |
| Usable Gates | — | 12,000 |
| Logic Array Blocks | — | 35 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Operating Temperature | — | 0C to +70C (commercial) |
| I/O Standards | — | 5.0 V TTL/CMOS compatible |
| Flip-Flops | — | 772 |
| MSL Level | — | [DATA_NEEDED: MSL level] |