EPM9560WC208-20C vs EPM9560WC208-20 Comparison

Detailed side-by-side comparison of EPM9560WC208-20C by Altera and EPM9560WC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560WC208-20C EPM9560WC208-20
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 9000 (EE PLD) —
Series EPM9560 —
Macrocells 560 560
Logic Array Blocks (LABs) 35 35
User I/O Pins 149 149
Propagation Delay (tPD) 20 ns —
Maximum Clock Frequency [DATA_NEEDED: fMAX value not in verified data] —
Process Technology CMOS, Electrically Erasable CMOS, EEPROM-based
Supply Voltage 3.3 V or 5 V (configurable I/O) —
Package 208-pin CQFP (Ceramic Quad Flat Pack) PQFP-208 (RQFP/WQFP)
Pin Count 208 —
Programming Interface JTAG BST (in-system programmable) —
Operating Temperature Grade Commercial (C suffix) —
Mounting Type Surface Mount (Ceramic QFP) Surface Mount
RoHS Status ROHS3 Compliant (per fpgalink listing) Non-compliant (legacy PQFP) [DATA_NEEDED: confirm from official doc]
Moisture Sensitivity Level MSL 3 (168 Hours) —
Family — MAX 9000
Device Type — CPLD (EPLD)
Maximum Propagation Delay (tPD) — 23.6 ns
Supply Voltage (VCCINT) — 5 V (typical, see datasheet)
I/O Voltage (VCCIO) — 3.3 V or 5 V (multi-voltage I/O)
In-System Programmability — Yes, JTAG BST (IEEE 1149.1)
Pin/Package Suffix — W = power PQFP; -20 = 23.6 ns speed grade
Operating Temperature — Commercial (0C to +70C) [DATA_NEEDED: exact temp grade]
Lead-Free — [DATA_NEEDED]
Halogen Free — [DATA_NEEDED]
MSL Level — [DATA_NEEDED]

Datasheets & Resources

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