H58G46AK6QX033 vs H58G66CK8BX147N Comparison
Detailed side-by-side comparison of H58G46AK6QX033 by SK hynix and H58G66CK8BX147N by SK hynix. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | H58G46AK6QX033 | H58G66CK8BX147N |
|---|---|---|
| Brand | SK hynix | SK hynix |
| Category | Mobile LPDDR4 | Memory ICs |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $34.60 |
| Memory Type | LPDDR5 (Low Power Double Data Rate 5) SDRAM | LPDDR5X SDRAM |
| Density | 16Gb (2 GB) | 64 Gbit (8 GB) |
| Organization | x16 | x8 (single channel) |
| Data Rate | 6400 Mbps per pin | — |
| Peak Bandwidth | 12.8 GB/s (x16 channel) | — |
| Interface | LPDDR5 (JEDEC) | LPDDR5/LPDDR5X protocol |
| Grade | Automotive | — |
| Supply Voltage | [DATA_NEEDED: core/I-O supply voltage] | — |
| Package Type | FBGA (ball grid array) | — |
| Ball Count | [DATA_NEEDED: package ball count] | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: Operating Temperature Range] |
| Mounting Type | Surface Mount (soldered BGA) | Surface Mount |
| Application Domain | Automotive ADAS, infotainment, industrial computing | Smartphone, AI edge, server-class mobile computing |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS Status] |
| AEC-Q100 | [DATA_NEEDED: AEC-Q100 qualification level] | — |
| Refresh | [DATA_NEEDED: refresh scheme] | — |
| Maximum Data Rate | — | 8533 Mbps |
| Supply Voltage Domain | — | 0.5 V to 1.8 V |
| Core Voltage Class | — | 1.05 V (LPDDR5/LPDDR5X class) |
| Package | — | 315-ball FBGA |
| Standard Compliance | — | JEDEC-compliant single-channel SDRAM (per SK hynix 315-ball FBGA specification) |
| Channel Configuration | — | Single channel (x8 or x16 capable family) |
| Power Management | — | Dynamic voltage and frequency scaling (DVFSC/DVFSQ) |
| Refresh Scheme | — | LPDDR5 per-bank / all-bank refresh |