LFE5UM5G-85F-8BG554I vs LFE5UM5G-85F8BG554I Comparison
Detailed side-by-side comparison of LFE5UM5G-85F-8BG554I by Lattice Semiconductor and LFE5UM5G-85F8BG554I by Lattice Semiconductor. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Lattice Semiconductor
LFE5UM5G-85F-8BG554I - 84K LUT ECP5-5G FPGA, 5G SERDES, BG554 | Lattice
LFE5UM5G-85F-8BG554I ✓ ActiveLattice Semiconductor
LFE5UM5G-85F8BG554I - 84K LUT, 5G SERDES ECP5 FPGA | Lattice
LFE5UM5G-85F8BG554I ✓ ActiveSpecification Comparison
| Parameter | LFE5UM5G-85F-8BG554I | LFE5UM5G-85F8BG554I |
|---|---|---|
| Brand | Lattice Semiconductor | Lattice Semiconductor |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $198.00 | $99.60 |
| Family | ECP5-5G (LatticeECP5-5G) | — |
| Logic Elements / Cells | 84,000 (83.6K LUTs) | — |
| Number of LABs/CLBs | 21,000 | — |
| Total Block RAM Bits | 3,833,856 (3,744 Kb) | — |
| Number of User I/O | 259 | — |
| Number of 5G SERDES Channels | [DATA_NEEDED: SERDES channel count for BG554 package] | — |
| Core Voltage (VCC) | 1.1 V | — |
| Auxiliary Voltage (VCCAUX) | 1.2 V | — |
| Process Technology | 40 nm CMOS | — |
| Speed Grade | -8 | — |
| Package | 554-ball caBGA (BG554) | 554-FBGA (caBGA) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | -40C to +100C (Industrial, I suffix) | -40C to +100C (Industrial) |
| MSL Level | 3 | — |
| Peak Reflow Temperature | 260 C (max 30 s) | 260C (30 s max, JESD-609 e1) |
| Terminal Finish | Tin-Silver-Copper (e1, JESD-609) | Tin Silver Copper (SnAgCu) |
| Halogen-Free / RoHS | Halogen-Free (Green), RoHS compliant | — |
| Configuration Interface | JTAG (IEEE 1149.1), SPI; supports Dual-Boot, Multi-Boot, TransFR | — |
| Design Software | Lattice Diamond | Lattice Diamond / Lattice Radiant |
| Product Family | — | ECP5-5G |
| Product Type | — | Field Programmable Gate Array (FPGA) |
| Logic Elements / LUT4 | — | 83,600 (84,000 nominal) |
| Embedded Block RAM (EBR) | — | 3,744 Kbit (3,833,856 bits) |
| Distributed RAM (LUT-based) | — | [DATA_NEEDED: distributed RAM in Kbit] |
| DSP / 18x18 Multipliers | — | 156 |
| SERDES Channels | — | 4 (5 Gbps multi-protocol) |
| SERDES Protocols | — | PCIe Gen1/Gen2, SGMII, CPRI, JESD204B, 5G multi-protocol |
| User I/O Count (this package) | — | 259 |
| Core Voltage | — | 1.2 V |
| Moisture Sensitivity Level (MSL) | — | 3 |
| Configuration | — | SPI, JTAG, sysCONFIG, dual-boot, multi-boot, TransFR |
| Boundary Scan | — | IEEE 1149.1 compliant |
| RoHS Status | — | Compliant (per Lattice product page) |