LFE5UM5G-85F-8BG554I vs LFE5UM5G-85F8BG554I Comparação

Comparação detalhada lado a lado de LFE5UM5G-85F-8BG554I por Lattice Semiconductor e LFE5UM5G-85F8BG554I por Lattice Semiconductor. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Lattice Semiconductor
LFE5UM5G-85F-8BG554I LFE5UM5G-85F-8BG554I - 84K LUT ECP5-5G FPGA, 5G SERDES, BG554 | Lattice

LFE5UM5G-85F-8BG554I - 84K LUT ECP5-5G FPGA, 5G SERDES, BG554 | Lattice

LFE5UM5G-85F-8BG554I ✓ Ativo
Lattice Semiconductor
LFE5UM5G-85F8BG554I LFE5UM5G-85F8BG554I - 84K LUT, 5G SERDES ECP5 FPGA | Lattice

LFE5UM5G-85F8BG554I - 84K LUT, 5G SERDES ECP5 FPGA | Lattice

LFE5UM5G-85F8BG554I ✓ Ativo

Comparação de especificações

Parâmetro LFE5UM5G-85F-8BG554I LFE5UM5G-85F8BG554I
Marca Lattice Semiconductor Lattice Semiconductor
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Ativo Ativo
Status do estoque In Stock In Stock
Preço unitário (USD) $198,00 $99,60
Family ECP5-5G (LatticeECP5-5G) —
Logic Elements / Cells 84,000 (83.6K LUTs) —
Number of LABs/CLBs 21,000 —
Total Block RAM Bits 3,833,856 (3,744 Kb) —
Number of User I/O 259 —
Number of 5G SERDES Channels [DATA_NEEDED: SERDES channel count for BG554 package] —
Core Voltage (VCC) 1.1 V —
Auxiliary Voltage (VCCAUX) 1.2 V —
Process Technology 40 nm CMOS —
Speed Grade -8 —
Encapsulamento 554-ball caBGA (BG554) 554-FBGA (caBGA)
Tipo de montagem Surface Mount Surface Mount
Temperatura de operação -40C to +100C (Industrial, I suffix) -40C to +100C (Industrial)
Nível MSL 3 —
Peak Reflow Temperature 260 C (max 30 s) 260C (30 s max, JESD-609 e1)
Terminal Finish Tin-Silver-Copper (e1, JESD-609) Tin Silver Copper (SnAgCu)
Halogen-Free / RoHS Halogen-Free (Green), RoHS compliant —
Configuration Interface JTAG (IEEE 1149.1), SPI; supports Dual-Boot, Multi-Boot, TransFR —
Design Software Lattice Diamond Lattice Diamond / Lattice Radiant
Product Family — ECP5-5G
Product Type — Field Programmable Gate Array (FPGA)
Logic Elements / LUT4 — 83,600 (84,000 nominal)
Embedded Block RAM (EBR) — 3,744 Kbit (3,833,856 bits)
Distributed RAM (LUT-based) — [DATA_NEEDED: distributed RAM in Kbit]
DSP / 18x18 Multipliers — 156
SERDES Channels — 4 (5 Gbps multi-protocol)
SERDES Protocols — PCIe Gen1/Gen2, SGMII, CPRI, JESD204B, 5G multi-protocol
User I/O Count (this package) — 259
Core Voltage — 1.2 V
Nível de sensibilidade à umidade (MSL) — 3
Configuration — SPI, JTAG, sysCONFIG, dual-boot, multi-boot, TransFR
Boundary Scan — IEEE 1149.1 compliant
Status RoHS — Compliant (per Lattice product page)

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