MPC8536AVTAQG vs MPC8536EAVTAQG Comparison
Detailed side-by-side comparison of MPC8536AVTAQG by NXP Semiconductors and MPC8536EAVTAQG by NXP Semiconductors. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
NXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndSpecification Comparison
| Parameter | MPC8536AVTAQG | MPC8536EAVTAQG |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Category | Microcontrollers | Microcontrollers |
| Lifecycle Status | Obsolete | NRND |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $171.00 | $218.75 |
| Processor Type | PowerPC e500 Microprocessor IC MPC85xx | — |
| Core Architecture | PowerPC e500 (Book-E compliant) | — |
| Number of Cores | 1 | 1 |
| Data Bus Width | 32-bit | 32 bit |
| Maximum Clock Frequency | 1.0 GHz | 1.0 GHz |
| Core Supply Voltage | 1.0 V | — |
| I/O Voltage | 1.8 V, 2.5 V, 3.3 V | — |
| Package / Case | 783-FCPBGA (29x29 mm) | — |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Memory Controller | DDR2, DDR3 (64-bit with ECC) | — |
| Ethernet | 2x 10/100/1000 Mbps (eTSEC, SGMII) | — |
| USB | USB 2.0 (ULPI interface) | — |
| Security Engine | AES, 3DES, SHA-1/SHA-2, MD-5, public-key acceleration | — |
| Datapath Acceleration | Hardware packet parsing, classification, policing | — |
| Local Bus | 16-bit data, 32-bit address | — |
| Operating Temperature Grade | Commercial | — |
| Processor Series | — | MPC85xx (PowerQUICC III) |
| Core | — | PowerPC e500, 32-bit |
| Package | — | 783-FCPBGA (29x29 mm) |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | — | [DATA_NEEDED: core/IO supply voltage] |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance] |