RTAX250SL-CG624E vs RTAX250S-CG624B Comparison

Detailed side-by-side comparison of RTAX250SL-CG624E by Microchip Technology and RTAX250S-CG624B by Microchip Technology. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Microchip Technology
RTAX250SL-CG624E RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip

RTAX250SL-CG624E ✓ Active
Microchip Technology
RTAX250S-CG624B RTAX250S-CG624B - 250K Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX250S-CG624B - 250K Gate Rad-Tolerant FPGA CCGA-624 | Microchip

RTAX250S-CG624B ✓ Active

Specification Comparison

Parameter RTAX250SL-CG624E RTAX250S-CG624B
Brand Microchip Technology Microchip Technology
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $1,375.00 $2,800.00
Family RTAX-S/SL Radiation-Tolerant FPGA —
System Gates 250000 250000 gates
Logic Cells (CLBs) 2816 2816 cells
Maximum Frequency 649 MHz —
Process Technology 0.15 um CMOS 0.15 um CMOS
Core Supply Voltage 1.5 V 1.5 V
Supply Voltage Tolerance +/-0.15 V —
Maximum Combinatorial Delay 0.93 ns —
Package 624-Pin CCGA (Ceramic Column Grid Array) —
Operating Temperature -55C to +125C -55C to +125C
Logic Family CMOS CMOS
Radiation Tolerance SEU-hardened registers; SEU rate < 10-10 errors/bit-day SEU rate < 10^-10 errors/bit-day; SEU-hardened registers
Embedded Memory Embedded SRAM with built-in FIFO control logic Embedded SRAM with built-in FIFO control logic
Clocking Segmentable clocks, chip-wide highway routing —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Programmability Live at power-up, true single-chip —
Maximum System Frequency — 649 MHz
Package Type — CCGA-624 (Ceramic Column Grid Array, 624 pins)
Configuration — One-time programmable antifuse, live at power-up
Product Family — RTAX-S / RTAX-SL Radiation-Tolerant FPGA
Architecture Basis — Microsemi Axcelerator commercial family
TMR Requirement — Eliminated for registers via SEU hardening
Speed Grade Option — Standard; -1 grade approximately 15% faster
I/O Supply Voltage — [DATA_NEEDED: I/O bank voltage]

Datasheets & Resources

Browse All Products Create BOM Request Quote