THS1230CDWRG4 vs THS1230CDWR Comparison
Detailed side-by-side comparison of THS1230CDWRG4 by Texas Instruments and THS1230CDWR by Texas Instruments. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Texas Instruments
THS1230CDWRG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWRG4 ✓ ActiveTexas Instruments
THS1230CDWR - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWR ✓ ActiveSpecification Comparison
| Parameter | THS1230CDWRG4 | THS1230CDWR |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Category | ADC/DAC | ADC/DAC |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $5.92 | $5.20 |
| Resolution | 12 bits | 12 bits |
| Sample Rate | 30 MSPS | 30 MSPS |
| Number of Inputs | 1 (single channel, configurable) | — |
| Input Configuration | Single-ended, single-ended w/ offset, differential | — |
| Analog Input Range | -2 V to +2 V | — |
| Supply Voltage | 3.3 V (single supply) | — |
| Supply Current | [DATA_NEEDED: typical supply current in mA] | — |
| Power-Down Mode | Yes | Yes (hardware PD pin) |
| Output Interface | Parallel CMOS | — |
| ADC Architecture | Pipelined | — |
| Operating Temperature | -40 C to +85 C | 0 °C to +70 °C (C-grade commercial) |
| Package | 28-SOIC (DW), 0.295 inch (7.50 mm) width | 28-pin SOIC (DW), 7.50 mm body width, tape and reel |
| Mounting Type | Surface Mount | Surface Mount |
| MSL Level | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| RoHS Status | Compliant | Compliant |
| Number of Channels | — | 1 |
| Supply Voltage (AVDD) | — | 3.3 V (single supply) |
| Architecture | — | Pipelined / multi-stage with digital error correction |
| Input Type | — | Configurable: single-ended, single-ended with offset, or differential |
| Analog Input Bandwidth | — | [DATA_NEEDED: analog input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fIN] |
| INL | — | [DATA_NEEDED: INL LSB] |
| DNL | — | [DATA_NEEDED: DNL LSB] |
| Power Dissipation | — | <250 mW at 30 MSPS (typical) |
| Digital Output | — | CMOS, parallel 12-bit |
| Reference | — | Internal (external reference option) |