THS1230CDWRG4 vs THS1230CDWR Vergleich
Detaillierter Direktvergleich von THS1230CDWRG4 von Texas Instruments und THS1230CDWR von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Texas Instruments
THS1230CDWRG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWRG4 ✓ AktivTexas Instruments
THS1230CDWR - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWR ✓ AktivSpezifikationsvergleich
| Parameter | THS1230CDWRG4 | THS1230CDWR |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $5,92 | $5,20 |
| Auflösung | 12 bits | 12 bits |
| Sample Rate | 30 MSPS | 30 MSPS |
| Number of Inputs | 1 (single channel, configurable) | — |
| Input Configuration | Single-ended, single-ended w/ offset, differential | — |
| Analog Input Range | -2 V to +2 V | — |
| Versorgungsspannung | 3.3 V (single supply) | — |
| Versorgungsstrom | [DATA_NEEDED: typical supply current in mA] | — |
| Power-Down Mode | Yes | Yes (hardware PD pin) |
| Output Interface | Parallel CMOS | — |
| ADC Architecture | Pipelined | — |
| Betriebstemperatur | -40 C to +85 C | 0 °C to +70 °C (C-grade commercial) |
| Gehäuse | 28-SOIC (DW), 0.295 inch (7.50 mm) width | 28-pin SOIC (DW), 7.50 mm body width, tape and reel |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| RoHS-Status | Compliant | Compliant |
| Number of Channels | — | 1 |
| Supply Voltage (AVDD) | — | 3.3 V (single supply) |
| Architecture | — | Pipelined / multi-stage with digital error correction |
| Input Type | — | Configurable: single-ended, single-ended with offset, or differential |
| Analog Input Bandwidth | — | [DATA_NEEDED: analog input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fIN] |
| INL | — | [DATA_NEEDED: INL LSB] |
| DNL | — | [DATA_NEEDED: DNL LSB] |
| Power Dissipation | — | <250 mW at 30 MSPS (typical) |
| Digital Output | — | CMOS, parallel 12-bit |
| Reference | — | Internal (external reference option) |