THS1230CDWRG4 vs THS1230CDWR Comparaison
Comparaison détaillée côte à côte de THS1230CDWRG4 par Texas Instruments et THS1230CDWR par Texas Instruments. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Texas Instruments
THS1230CDWRG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWRG4 ✓ ActifTexas Instruments
THS1230CDWR - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWR ✓ ActifComparaison des spécifications
| Paramètre | THS1230CDWRG4 | THS1230CDWR |
|---|---|---|
| Marque | Texas Instruments | Texas Instruments |
| Catégorie | ADC/DAC | ADC/DAC |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,92 | $5,20 |
| Résolution | 12 bits | 12 bits |
| Sample Rate | 30 MSPS | 30 MSPS |
| Number of Inputs | 1 (single channel, configurable) | — |
| Input Configuration | Single-ended, single-ended w/ offset, differential | — |
| Analog Input Range | -2 V to +2 V | — |
| Tension d'alimentation | 3.3 V (single supply) | — |
| Courant d'alimentation | [DATA_NEEDED: typical supply current in mA] | — |
| Power-Down Mode | Yes | Yes (hardware PD pin) |
| Output Interface | Parallel CMOS | — |
| ADC Architecture | Pipelined | — |
| Température de fonctionnement | -40 C to +85 C | 0 °C to +70 °C (C-grade commercial) |
| Boîtier | 28-SOIC (DW), 0.295 inch (7.50 mm) width | 28-pin SOIC (DW), 7.50 mm body width, tape and reel |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Statut RoHS | Compliant | Compliant |
| Number of Channels | — | 1 |
| Supply Voltage (AVDD) | — | 3.3 V (single supply) |
| Architecture | — | Pipelined / multi-stage with digital error correction |
| Input Type | — | Configurable: single-ended, single-ended with offset, or differential |
| Analog Input Bandwidth | — | [DATA_NEEDED: analog input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fIN] |
| INL | — | [DATA_NEEDED: INL LSB] |
| DNL | — | [DATA_NEEDED: DNL LSB] |
| Power Dissipation | — | <250 mW at 30 MSPS (typical) |
| Digital Output | — | CMOS, parallel 12-bit |
| Reference | — | Internal (external reference option) |