XC2C32A-6CP56C vs XC2C32A-4CP56C Comparison
Detailed side-by-side comparison of XC2C32A-6CP56C by Xilinx and XC2C32A-4CP56C by AMD. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | XC2C32A-6CP56C | XC2C32A-4CP56C |
|---|---|---|
| Brand | Xilinx | AMD |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Device Type | CoolRunner-II complex programmable logic device (CPLD) | CoolRunner-II complex programmable logic device |
| Macrocell Count | 32 macrocells | — |
| Logic Gate Count | 750 gates | — |
| User I/O Count | 33 pins | — |
| Logic Array Blocks | 2 logic array blocks | — |
| Maximum Operating Frequency | 200 MHz | — |
| Internal Frequency | 450 MHz | 450 MHz |
| Propagation Delay | 4 ns | 3.8 ns |
| Minimum Pin-to-Pin Logic Delay | 3.0 ns | — |
| Quiescent Current | 12 µA | 12 µA minimum |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Internal Supply Voltage Range | 1.7 V to 1.9 V | — |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS |
| Logic Family | CMOS | CMOS |
| Package | CSP-56, 6 x 6 mm, 0.50 mm pitch | 56-pin CSPBGA, 6 x 6 mm, 0.50 mm pitch |
| Total Package Pins | 56 balls | — |
| Mounting Type | Surface mount | — |
| Programming Support | In-system programmable | — |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Macrocells | — | 32 macrocells |
| Maximum Pin-to-Pin Logic Delay | — | 3.0 ns |
| User I/Os | — | 33 pins |
| Total Pins | — | 56 pins |
| Terminal Type | — | Ball |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Lead-Free Status | — | Lead Free |
| Programming Interface | — | [DATA_NEEDED: programming interface details] |