XC2C32A-6CP56C vs XC2C32A-4CP56C 对比
详细并排对比 XC2C32A-6CP56C 出自 Xilinx 和 XC2C32A-4CP56C 出自 AMD。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | XC2C32A-6CP56C | XC2C32A-4CP56C |
|---|---|---|
| 品牌 | Xilinx | AMD |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | 有效 | 有效 |
| Device Type | CoolRunner-II complex programmable logic device (CPLD) | CoolRunner-II complex programmable logic device |
| Macrocell Count | 32 macrocells | — |
| Logic Gate Count | 750 gates | — |
| User I/O Count | 33 pins | — |
| Logic Array Blocks | 2 logic array blocks | — |
| Maximum Operating Frequency | 200 MHz | — |
| Internal Frequency | 450 MHz | 450 MHz |
| Propagation Delay | 4 ns | 3.8 ns |
| Minimum Pin-to-Pin Logic Delay | 3.0 ns | — |
| 静态电流 | 12 µA | 12 µA minimum |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Internal Supply Voltage Range | 1.7 V to 1.9 V | — |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS |
| Logic Family | CMOS | CMOS |
| 封装 | CSP-56, 6 x 6 mm, 0.50 mm pitch | 56-pin CSPBGA, 6 x 6 mm, 0.50 mm pitch |
| Total Package Pins | 56 balls | — |
| 安装类型 | Surface mount | — |
| Programming Support | In-system programmable | — |
| 工作温度范围 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Macrocells | — | 32 macrocells |
| Maximum Pin-to-Pin Logic Delay | — | 3.0 ns |
| User I/Os | — | 33 pins |
| Total Pins | — | 56 pins |
| Terminal Type | — | Ball |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Lead-Free Status | — | Lead Free |
| Programming Interface | — | [DATA_NEEDED: programming interface details] |