XC2C64A-7CP56C vs XC2C64A-5CP56C Comparison

Detailed side-by-side comparison of XC2C64A-7CP56C by AMD and XC2C64A-5CP56C by AMD. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

AMD
XC2C64A-5CP56C XC2C64A-5CP56C - 64-Macrocell 1.8V CPLD | AMD

XC2C64A-5CP56C - 64-Macrocell 1.8V CPLD | AMD

XC2C64A-5CP56C ✓ Active

Specification Comparison

Parameter XC2C64A-7CP56C XC2C64A-5CP56C
Brand AMD AMD
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Device Type CoolRunner-II complex programmable logic device CoolRunner-II complex programmable logic device (CPLD)
Macrocell Count 64 macrocells —
Equivalent Logic Capacity 1.5K gates —
Internal Frequency 333 MHz 333 MHz
Propagation Delay 5 ns —
Pin-to-Pin Logic Delay 4.6 ns —
User I/O Count 45 I/Os —
Logic Family CMOS CMOS
Process Technology 0.18 µm CMOS 0.18 micron CMOS
Core Supply Voltage 1.8 V —
Quiescent Current 15 µA 15 A as reported in the verified search summary
Package Type CSP-56, 6 x 6 mm, 0.50 mm pitch 56-ball CSP/LFBGA
Pin Count 56 pins —
Mounting Type Chip-scale surface-mount package —
Operating Temperature [DATA_NEEDED: operating temperature range] —
RoHS Compliance [DATA_NEEDED: RoHS status] —
REACH Compliance [DATA_NEEDED: REACH status] —
AEC-Q100 Qualification [DATA_NEEDED: AEC-Q100 status] [DATA_NEEDED: AEC-Q100 qualification status]
Number of Macrocells — 64
Logic Elements or Blocks — 4
User I/O Pins — 45
Total Terminals — 56
Maximum Pin-to-Pin Propagation Delay — 4.6 ns
Internal Supply Voltage Range — 1.7 V to 1.9 V
System Optimization Voltage — 1.8 V
Programmable Type — In-system programmable
Package Dimensions — 6 x 6 mm
Ball Pitch — 0.50 mm
Temperature Grade — Commercial
RoHS Status — [DATA_NEEDED: RoHS status]
REACH Status — [DATA_NEEDED: REACH status]
Operating Temperature Range — [DATA_NEEDED: operating temperature range]

Datasheets & Resources

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