XC3090L-8PC84BKJ vs XC3090L-8PCG84C Comparison
Detailed side-by-side comparison of XC3090L-8PC84BKJ by Xilinx and XC3090L-8PCG84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090L-8PC84BKJ
XC3090L-8PC84BKJ - XC3000L 5V FPGA 84-Pin PLCC | AMD Xilinx
XC3090L-8PC84BKJ ObsoleteXilinx
XC3090L-8PCG84C
XC3090L-8PCG84C - 84-Pin PLCC FPGA | Xilinx XC3000 Family
XC3090L-8PCG84C β Last Time BuySpecification Comparison
| Parameter | XC3090L-8PC84BKJ | XC3090L-8PCG84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.20 | $26.10 |
| Family | XC3000L Low-Voltage Logic Cell Array | XC3000A/L Series FPGA |
| Logic Cells | 320 | β |
| Usable Gates | 6,000 | β |
| Configuration Memory | 64,160 bits | β |
| Maximum User I/O | 144 | β |
| Supply Voltage (Vcc) | 3.0 V to 3.6 V (low-voltage) | β |
| Speed Grade | -8 (approx. 70 MHz toggle) | -8 (moderate) |
| Process Technology | 5 ns CMOS SRAM | [DATA_NEEDED: process node] |
| Configuration Method | Serial/parallel SRAM, in-system reconfigurable | β |
| Boundary Scan | IEEE 1149.1 (JTAG) compliant | β |
| Package | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) | 84-pin PLCC (J-Lead, PCG84) |
| Operating Temperature | 0C to +70C (commercial, C suffix) | 0 C to +70 C (commercial 'C' suffix) |
| Mounting Type | Through-hole (PLCC socket) | Surface Mount (PLCC J-Lead) |
| MSL Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| RoHS Status | unknown - legacy windowed ceramic package | unknown |
| Configuration Pins | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT | β |
| Logic Cells / CLBs | β | 70 Configurable Logic Blocks |
| Gate Count | β | 6,400 gates (typical) |
| Configuration Program Store | β | 64,160 bits |
| User I/O Pins | β | 70 (maximum) |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Configuration Modes | β | Serial master/slave, parallel master/slave, peripheral mode |
| JTAG / Boundary Scan | β | IEEE 1149.1 compliant |
| Configuration Clock Range | β | [DATA_NEEDED: CCLK frequency range] |
| Lead-Free | β | unknown |
| Programming Technology | β | SRAM-based, in-system reconfigurable |