XC3090LTM-100PC84C vs XC3090L-100PC84C Comparison
Detailed side-by-side comparison of XC3090LTM-100PC84C by Xilinx and XC3090L-100PC84C by Xilinx. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Xilinx
XC3090LTM-100PC84C
XC3090LTM-100PC84C - 6K Gate, 320-Cell FPGA 5V 84-PLCC | Xilinx
XC3090LTM-100PC84C ObsoleteXilinx
XC3090L-100PC84C
XC3090L-100PC84C - XC3000 FPGA 6K Gates 100MHz PLCC-84 | Xilinx
XC3090L-100PC84C NrndSpecification Comparison
| Parameter | XC3090LTM-100PC84C | XC3090L-100PC84C |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $41.40 | $15.20 |
| Manufacturer | Xilinx | β |
| Series | XC3000L Logic Cell Array Family | XC3090L (Low Power) |
| Family | XC3090 | XC3000 |
| Logic Cells / CLBs | 320 Configurable Logic Blocks | 320 Configurable Logic Blocks |
| Typical Gate Count | 5,000 to 6,000 gates | β |
| Technology | 5V CMOS, SRAM-based configuration | β |
| Performance Grade | 100 MHz | β |
| Package | 84-pin PLCC (PC84) | 84-pin PLCC (PC84) |
| Terminal Form | J-Lead (Surface Mount) | β |
| Package Code | QCCJ (Plastic Leaded Chip Carrier) | PC84C |
| Operating Temperature Grade | Commercial | β |
| Configuration Memory | SRAM (volatile, requires external bitstream) | β |
| I/O Standard | 5V CMOS / TTL compatible | β |
| Programming Method | External configuration PROM or microcontroller bitstream load | β |
| RoHS Status | [DATA_NEEDED: legacy device, pre-RoHS era] | [DATA_NEEDED: rohs_status] |
| Lifecycle Status | Obsolete / Discontinued by manufacturer | β |
| Gate Count (typical) | β | 5,000 to 6,000 gates |
| Maximum Operating Frequency | β | 100 MHz |
| Speed Grade | β | -100 |
| Process Technology | β | CMOS, 5 micron |
| Supply Voltage | β | 5 V |
| Mounting Type | β | Through-Hole / Socket (PLCC) |
| Operating Temperature | β | Commercial (0C to +70C) |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |
| Configuration Method | β | Xilinx XACT bitstream |
| MSL Level | β | [DATA_NEEDED: msl_level] |
| Lead Free | β | [DATA_NEEDED: lead_free] |