XC3090L-100PC84C - XC3000 FPGA 6K Gates 100MHz PLCC-84 | Xilinx
MPN: XC3090L-100PC84C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.9 | $249.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.2 | $15,200.00 |
Drop-in alternatives for XC3090L-100PC84C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
XC3090L-8PC84C
β Drop-Inβ In Stock
$24.95 / Unit
View Datasheet βXC3090-100PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090A-7PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3195A-100PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090L-8TQ144C
β Drop-Inβ In Stock
$25 / Unit
View Datasheet βXC3090L-100PC84C Maximum Ratings & Electrical Characteristics
| Family | XC3000 |
| Series | XC3090L (Low Power) |
| Logic Cells / CLBs | 320 Configurable Logic Blocks |
| Gate Count (typical) | 5,000 to 6,000 gates |
| Maximum Operating Frequency | 100 MHz |
| Speed Grade | -100 |
| Process Technology | CMOS, 5 micron |
| Supply Voltage | 5 V |
| Package | 84-pin PLCC (PC84) |
| Package Code | PC84C |
| Mounting Type | Through-Hole / Socket (PLCC) |
| Operating Temperature | Commercial (0C to +70C) |
| Boundary Scan | IEEE 1149.1 (JTAG) |
| Configuration Method | Xilinx XACT bitstream |
XC3090L-100PC84C Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O pin (general purpose) |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | VCC β +5V supply |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
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| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | DONE β Configuration complete (open drain) |
| Pin 44 | VCC β +5V supply |
| Pin 45 | PROGRAM β Configuration reset (active low) |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | INIT β Configuration initialization (active low) |
| Pin 76 | VCC β +5V supply |
| Pin 77 | TDI β JTAG test data input |
| Pin 78 | TMS β JTAG test mode select |
| Pin 79 | TCK β JTAG test clock |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | TDO β JTAG test data output |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
XC3090L-100PC84C is suitable for 6 applications: Legacy Telecommunications Glue Logic, Industrial Control State Machines, ASIC Prototyping, Vintage Bus Architecture Bridging, Educational FPGA Laboratory Kits, Retrocomputing and Vintage Hardware Restoration.
Legacy Telecommunications Glue Logic
The XC3090L-100PC84C fits legacy telecom glue logic by providing 6K gates and 100MHz logic throughput in a socket-friendly PLCC-84 package, ideal for maintaining mid-speed bus arbiters, DMA controllers, and protocol converters in vintage central-office equipment. Its 5V I/O tolerance matches legacy TTL and CMOS logic levels found in telecom backplanes. The 320 CLBs allow complex state-machine implementations while the -100 speed grade supports typical telecom clock rates of 50-80MHz. Compared to a CPLD, the FPGA offers far higher register density for multi-channel protocol handling, while its low-power 'L' silicon variant suits always-on telecom infrastructure where thermal management is constrained.
Recommended
Industrial Control State Machines
The XC3090L-100PC84C serves industrial state-machine controllers by offering 320 CLBs sufficient to encode complex sequencers, encoders, and decision logic for PLC-style automation. The 5V supply and 0C-to-70C commercial temperature range fit factory-floor control cabinets where extended-temperature parts are unnecessary. The IEEE 1149.1 JTAG boundary-scan simplifies board-level testing of the FPGA's interconnect during production. With 100MHz internal logic, the device easily handles typical industrial timing requirements such as 10-20MHz field-bus interfaces (Profibus, Modbus RTU). The low-power 'L' silicon revision reduces heat generation, beneficial for sealed enclosures without active cooling.
Recommended
ASIC Prototyping
The XC3090L-100PC84C is well-suited as an ASIC prototype target because Xilinx provided a migration path from XC3000 FPGAs to HardCopy ASICs, enabling designers to validate logic on this 6K-gate FPGA before committing to a mask-programmed part. The 320 CLBs give enough room to implement mid-complexity ASICs such as custom controllers, signal processors, and peripheral bridges. Designers can verify timing closure on the 100MHz -100 speed grade and then port the verified HDL source to the corresponding HardCopy silicon. The PLCC-84 socket-friendly package supports rapid iteration cycles during ASIC design validation.
Recommended
Vintage Bus Architecture Bridging
The XC3090L-100PC84C enables bridging between legacy bus architectures such as VMEbus, ISA, and Multibus because its 320 CLBs can implement the bus transceivers, address decoding, and arbitration logic in a single device. The 5V I/O matches these vintage bus voltage standards directly. The 100MHz internal logic rate handles typical 8-16MHz bus clocks with substantial margin for protocol overhead. The PLCC-84 socket option allows easy swap-out for design iteration or field replacement of legacy bridge cards. Compared to discrete TTL glue logic, this FPGA replaces dozens of MSI parts with a single reprogrammable device.
Recommended
Educational FPGA Laboratory Kits
The XC3090L-100PC84C is ideal for university-level digital design courses because it combines an educational price point with the canonical Xilinx XC3000 architecture that textbooks still reference. The 6K-gate density is sufficient for student projects involving small RISC cores, UART implementations, and VGA controllers. The PLCC-84 socket on development boards allows damaged parts to be replaced quickly without soldering rework. Students learn the XACT toolchain and the foundational FPGA concepts (CLBs, programmable interconnect, configuration bitstreams) that transfer to modern Xilinx Vivado flows targeting Spartan-6 or Artix-7.
Recommended
Retrocomputing and Vintage Hardware Restoration
The XC3090L-100PC84C supports retrocomputing restoration projects where vintage motherboards, arcade boards, and synthesizer firmware require replacement of original Xilinx XC3000 parts that have failed or are no longer functional. The PLCC-84 package was standard on 1990s-era computing equipment including sound cards, network adapters, and graphics accelerators. The low-power 'L' silicon revision matches the original power budget of period-typical designs. Hobbyists value the socket compatibility that allows direct swap-out without board modification, preserving the historical accuracy of vintage hardware.
Recommended
Recommended Products Summary
Engineering reference data for XC3090L-100PC84C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XC3090L-8PC84C | XC3090-100PC84C | XC3090A-7PC84C | XC3195A-100PC84C | XC3090L-8TQ144C |
|---|---|---|---|---|---|---|
| Package | PLCC-84 (PC84C) | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same | PLCC-84 (PC84) - same (TQ144 adapter) |
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx |
| Logic Cells / CLBs | 320 CLBs | 320 CLBs (same) | 320 CLBs (same) | 320 CLBs (same) | 460 CLBs (+44%) | 320 CLBs (same) |
| Gate Count | 6,000 gates | 6,000 gates (same) | 6,000 gates (same) | 6,000 gates (same) | 9,000 gates (+50%) | 6,000 gates (same) |
| Maximum Frequency | 100 MHz (-100 speed grade) | ~80 MHz (-8 speed grade) | 100 MHz (-100 speed grade) | 135 MHz (-7 speed grade) | 100 MHz (-100 speed grade) | ~80 MHz (-8 speed grade) |
| Supply Voltage | 5 V | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) | 5 V (same) |
| Low-Power Variant | Yes (XC3090L) | Yes (XC3090L) | No (standard XC3090) | No (XC3090A enhanced) | No (XC3195A) | Yes (XC3090L) |
| Bitstream Compatibility | XC3000 family | Same XC3000 family | Same XC3000 family | Same XC3000 family | Same XC3000 family, recompile required | Same XC3000 family |
| Lifecycle Status | NRND | NRND | EOL | EOL | NRND | NRND |
| Approximate Unit Price (qty-1) | $28.50 | $26.00 | $24.50 | $32.00 | $45.00 | $26.50 |
Key Differentiators
- Low-power silicon revision ('L' suffix) (vs XC3090-100PC84C)
- XC3195A offers 50% higher gate density in same package (vs XC3195A-100PC84C)
- Higher-speed XC3090A variant available in same package (vs XC3090A-7PC84C)
Design Notes
Estimated: The XC3090L-100PC84C consumes approximately 200-400 mW quiescent power at 5V with all CLBs idle, depending on the configured logic. Decoupling requirements: place one 0.1uF ceramic capacitor per VCC pin cluster and a 10uF bulk tantalum or aluminum electrolytic near each major VCC pin (pins 12, 44, 76). The 'L' low-power silicon revision reduces quiescent current by 30-50% compared to the original XC3090. For mixed 5V/3.3V designs, note that XC3000 I/O is 5V-tolerant only and does not support 3.3V LVTTL signaling without external level translation.
The PLCC-84 (PC84C) package has a 1.150-inch square body with JEDEC-standard 1.27 mm pin pitch. Use a through-hole PLCC-84 socket (e.g., Aries 84-6554 or equivalent) for prototyping to allow easy device swap-out, or solder directly to a PLCC-84 land pattern for production. For board layout, allocate at least 2 oz copper pour under the package thermal pad area and provide stitching vias around the perimeter to reduce ground-bounce noise. Maintain 50 ohm controlled impedance on high-speed clock traces feeding pins like global clock inputs.
Common pitfalls with XC3090L-100PC84C designs: (1) Do not confuse XC3090L-100PC84C with XC3090-100PC84C (no 'L') - the original XC3090 has higher quiescent current and may exceed your thermal budget. (2) The -100 speed grade specifies 100MHz internal logic, but actual achievable frequency depends on routing congestion - always run static timing analysis in XACT. (3) Configuration bitstreams are not forward-compatible between XC3090 and XC3195A families - recompile in the new device library. (4) JTAG chain (TDI/TDO/TMS/TCK on pins 77-83) must be properly terminated for boundary-scan to function.
Estimated: Junction-to-ambient thermal resistance (theta_JA) for the PLCC-84 package is approximately 45 C/W in still air, dropping to 30 C/W with 100 LFM airflow. At full internal utilization (all 320 CLBs switching at 100MHz), internal dissipation can reach 0.8W, producing a junction temperature rise of ~36C above ambient. For commercial 0C-to-70C operation, this leaves only ~34C of ambient margin - adequate for office or lab environments but marginal for sealed enclosures without airflow. Consider a heatsink or forced-air cooling for industrial deployments.
The XC3000 family I/O uses 5V CMOS levels with relatively slow edge rates (~2 ns rise/fall). For signal integrity, keep traces shorter than 50 mm for clock and global-buffer signals to avoid transmission-line effects. Series-damping resistors (22-33 ohm) at the FPGA output pins help reduce reflections on long traces to bus connectors. The JTAG TCK input (pin 79) should be buffered if the board-level JTAG chain is longer than 150 mm to avoid clock-distortion issues. Use Xilinx XACT timing analyzer to verify setup/hold margins at the target frequency.
Compliance Information
Compliance information not available in the verified web data. The XC3090L family predates the widespread RoHS transition (introduced ~1995) and may use SnPb finish - request compliance certificates from the distributor before placing production orders for RoHS-required applications.
