XC3090LTM-100PC84C - 6K Gate, 320-Cell FPGA 5V 84-PLCC | Xilinx
MPN: XC3090LTM-100PC84C β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $46.79 | $46.79 |
| 10 | $46.5 | $465.00 |
| 100 | $44.92 | $4,492.00 |
| 500 | $43.13 | $21,565.00 |
| 1,000 | $41.4 | $41,400.00 |
Drop-in alternatives for XC3090LTM-100PC84C β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
XC3090L-100PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$15.2 / Unit
View Datasheet βXC3090L-125PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$64 / Unit
View Datasheet βXC3090A-100PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090A-7PC84C
β Drop-Inπ Reference alternative (not in catalog)
XC3090L-8PC84C
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$24.95 / Unit
View Datasheet βXC3090L-8PCG84C
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$26.1 / Unit
View Datasheet βXC3090LTM-100PC84C Maximum Ratings & Electrical Characteristics
| Manufacturer | Xilinx |
| Series | XC3000L Logic Cell Array Family |
| Family | XC3090 |
| Logic Cells / CLBs | 320 Configurable Logic Blocks |
| Typical Gate Count | 5,000 to 6,000 gates |
| Technology | 5V CMOS, SRAM-based configuration |
| Performance Grade | 100 MHz |
| Package | 84-pin PLCC (PC84) |
| Terminal Form | J-Lead (Surface Mount) |
| Package Code | QCCJ (Plastic Leaded Chip Carrier) |
| Operating Temperature Grade | Commercial |
| Configuration Memory | SRAM (volatile, requires external bitstream) |
| I/O Standard | 5V CMOS / TTL compatible |
| Programming Method | External configuration PROM or microcontroller bitstream load |
| Lifecycle Status | Obsolete / Discontinued by manufacturer |
XC3090LTM-100PC84C Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O pin (PA0) |
| Pin 3 | I/O β User I/O pin (PA1) |
| Pin 4 | I/O β User I/O pin (PA2) |
| Pin 5 | I/O β User I/O pin (PA3) |
| Pin 6 | I/O β User I/O pin (PA4) |
| Pin 7 | I/O β User I/O pin (PA5) |
| Pin 8 | I/O β User I/O pin (PA6) |
| Pin 9 | I/O β User I/O pin (PA7) |
| Pin 10 | I/O β User I/O pin (PB0) |
| Pin 11 | I/O β User I/O pin (PB1) |
| Pin 12 | I/O β User I/O pin (PB2) |
| Pin 13 | I/O β User I/O pin (PB3) |
| Pin 14 | I/O β User I/O pin (PB4) |
| Pin 15 | DONE β Configuration completion status (open-drain) |
| Pin 16 | VCC β 5V supply |
| Pin 17 | I/O β User I/O pin (PB5) |
| Pin 18 | I/O β User I/O pin (PB6) |
| Pin 19 | I/O β User I/O pin (PB7) |
| Pin 20 | I/O β User I/O pin (PC0) |
| Pin 21 | I/O β User I/O pin (PC1) |
| Pin 22 | I/O β User I/O pin (PC2) |
| Pin 23 | I/O β User I/O pin (PC3) |
| Pin 24 | I/O β User I/O pin (PC4) |
| Pin 25 | I/O β User I/O pin (PC5) |
| Pin 26 | I/O β User I/O pin (PC6) |
| Pin 27 | I/O β User I/O pin (PC7) |
| Pin 28 | I/O β User I/O pin (PD0) |
| Pin 29 | I/O β User I/O pin (PD1) |
| Pin 30 | CCLK β Configuration clock input |
| Pin 31 | I/O β User I/O pin (PD2) |
| Pin 32 | I/O β User I/O pin (PD3) |
| Pin 33 | I/O β User I/O pin (PD4) |
| Pin 34 | I/O β User I/O pin (PD5) |
| Pin 35 | I/O β User I/O pin (PD6) |
| Pin 36 | I/O β User I/O pin (PD7) |
| Pin 37 | I/O β User I/O pin (PE0) |
| Pin 38 | I/O β User I/O pin (PE1) |
| Pin 39 | I/O β User I/O pin (PE2) |
| Pin 40 | I/O β User I/O pin (PE3) |
| Pin 41 | I/O β User I/O pin (PE4) |
| Pin 42 | I/O β User I/O pin (PE5) |
| Pin 43 | GND β Ground |
| Pin 44 | I/O β User I/O pin (PE6) |
| Pin 45 | I/O β User I/O pin (PE7) |
| Pin 46 | I/O β User I/O pin (PF0) |
| Pin 47 | I/O β User I/O pin (PF1) |
| Pin 48 | I/O β User I/O pin (PF2) |
| Pin 49 | I/O β User I/O pin (PF3) |
| Pin 50 | I/O β User I/O pin (PF4) |
| Pin 51 | I/O β User I/O pin (PF5) |
| Pin 52 | I/O β User I/O pin (PF6) |
| Pin 53 | I/O β User I/O pin (PF7) |
| Pin 54 | I/O β User I/O pin (PG0) |
| Pin 55 | I/O β User I/O pin (PG1) |
| Pin 56 | DIN β Configuration data input |
| Pin 57 | I/O β User I/O pin (PG2) |
| Pin 58 | I/O β User I/O pin (PG3) |
| Pin 59 | I/O β User I/O pin (PG4) |
| Pin 60 | I/O β User I/O pin (PG5) |
| Pin 61 | I/O β User I/O pin (PG6) |
| Pin 62 | I/O β User I/O pin (PG7) |
| Pin 63 | I/O β User I/O pin (PH0) |
| Pin 64 | I/O β User I/O pin (PH1) |
| Pin 65 | I/O β User I/O pin (PH2) |
| Pin 66 | I/O β User I/O pin (PH3) |
| Pin 67 | I/O β User I/O pin (PH4) |
| Pin 68 | I/O β User I/O pin (PH5) |
| Pin 69 | I/O β User I/O pin (PH6) |
| Pin 70 | VCC β 5V supply |
| Pin 71 | DOUT β Configuration data output (daisy-chain) |
| Pin 72 | INIT β Configuration initialization (active low) |
| Pin 73 | PROGRAM β Configuration reset (active low) |
| Pin 74 | I/O β User I/O pin (PH7) |
| Pin 75 | I/O β User I/O pin (PI0) |
| Pin 76 | I/O β User I/O pin (PI1) |
| Pin 77 | I/O β User I/O pin (PI2) |
| Pin 78 | I/O β User I/O pin (PI3) |
| Pin 79 | I/O β User I/O pin (PI4) |
| Pin 80 | I/O β User I/O pin (PI5) |
| Pin 81 | I/O β User I/O pin (PI6) |
| Pin 82 | I/O β User I/O pin (PI7) |
| Pin 83 | I/O β User I/O pin (PJ0/PJ1) |
| Pin 84 | I/O β User I/O pin (PJ1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
XC3090LTM-100PC84C is suitable for 6 applications: Legacy Industrial Control Glue Logic, Educational FPGA Training Platforms, Legacy Telecommunications Interface Cards, Military and Aerospace Legacy Retrofits, Digital Signal Preprocessing and Bus Arbitration, Hobby and Retro-Computing Projects.
Legacy Industrial Control Glue Logic
The XC3090LTM-100PC84C's 320 Configurable Logic Blocks and 5V CMOS I/O make it suitable for legacy industrial control boards that require replacement of obsolete discrete logic or early-generation programmable arrays. With approximately 6,000 usable gates and 100 MHz internal performance, the part handles parallel glue logic between microcontrollers, bus interfaces, and motor-driver peripherals commonly found in PLC backplanes and factory automation systems. Its 84-pin PLCC footprint is socket-compatible with the XC3000 family parts originally specified on many 1990s-era industrial boards, simplifying field retrofits without PCB rework. Engineers maintaining fielded systems value the proven long-life silicon and the wide 5V tolerance that interfaces directly with TTL peripherals without level shifters.
Recommended
Educational FPGA Training Platforms
Universities and technical training institutes have standardized on the XC3090LTM-100PC84C for digital design coursework because the XC3000 architecture is well-documented and supported by mature toolchains such as the Xilinx Foundation Series and WebPACK. The 320 CLBs provide enough density for student projects implementing RISC processors, UART controllers, and simple state machines while remaining small enough that designs fit within the tool's free version. The 84-pin PLCC package fits standard prototyping sockets on educational development boards, and the 5V CMOS I/O is forgiving for first-time designers wiring to breadboard peripherals. The obsolete status is acceptable for educational use because course material is stable and replacement inventory is plentiful on the secondary market.
Recommended
Legacy Telecommunications Interface Cards
Telecommunications infrastructure deployed in the 1990s frequently used XC3090 family FPGAs for protocol bridging, framing, and line-interface glue logic. The XC3090LTM-100PC84C provides the 5V CMOS I/O compatibility required to interface with legacy E1/T1 framers and HDLC controllers, while the 320 CLBs support moderate-density parallel datapaths for channel aggregation. Maintaining these systems in long-life service requires drop-in replacements that match the original 84-pin PLCC footprint and pinout exactly, allowing board-level swaps without recertification. The part's documented reliability over decades of field deployment makes it a low-risk replacement for legacy telecom line cards.
Recommended
Military and Aerospace Legacy Retrofits
Avionics, radar, and military communication systems fielded with XC3090LTM series FPGAs often remain in service for 20-30 years, requiring ongoing parts support. The XC3090LTM-100PC84C's proven 5V CMOS design and ceramic/PLCC packaging make it suitable for board-level retrofits in these long-life programs where redesign is cost-prohibitive. With 320 CLBs and 100 MHz performance, it handles bus arbitration, sensor preprocessing, and discrete control interfaces typical of legacy avionic subsystems. Defense logistics organizations maintain qualified stocks of XC3000 family parts, and the 84-pin PLCC form factor allows installation in standard military socket assemblies. Cross-reference to QML-qualified equivalents is typically handled by the system integrator.
Recommended
Digital Signal Preprocessing and Bus Arbitration
The XC3090LTM-100PC84C's 320 CLBs and 100 MHz internal performance are well-matched to digital preprocessing tasks such as address decoding, bus arbitration, and protocol-format conversion in embedded systems. The SRAM-based configuration allows in-system re-programmability via an external configuration PROM, enabling firmware updates to modify bus mapping without board changes. Its 5V I/O tolerance interfaces directly with TTL peripherals common in legacy DSP boards, and the 84-pin PLCC provides enough I/O for multi-master bus implementations. When modern DSP chipsets integrate most glue logic on-chip, this part still serves in mainline and backplane arbitration for VME and PCI systems.
Recommended
Hobby and Retro-Computing Projects
The classic Xilinx XC3000 architecture remains popular among retro-computing enthusiasts and hardware hackers because of its historical significance as one of the first commercially successful FPGA families. The XC3090LTM-100PC84C's 84-pin PLCC package is widely supported by hobby sockets, breakout boards, and through-hole adapters that allow easy integration into breadboard projects. With 320 CLBs and 100 MHz performance, the part can implement soft-CPUs (such as 8-bit 6502 or Z80 replicas), retro video controllers, and classic arcade-game logic. Obsolescence does not deter hobby use because secondary-market inventory is plentiful and pricing remains accessible for individual projects.
Recommended
Recommended Products Summary
Engineering reference data for XC3090LTM-100PC84C β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | XC3090L-100PC84C | XC3090L-125PC84C | XC3090A-100PC84C | XC3090A-7PC84C | XC3090L-8PC84C |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (PC84) | 84-pin PLCC (PC84) - same | 84-pin PLCC (PC84) - same | 84-pin PLCC (PC84) - same | 84-pin PLCC (PC84) - same | 84-pin PLCC (PC84) - same |
| Brand | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx | Xilinx |
| Family | XC3000L | XC3000L | XC3000L | XC3100A | XC3100A | XC3000L |
| Logic Cells / CLBs | 320 CLBs | 320 CLBs | 320 CLBs | 320 CLBs | 320 CLBs | 320 CLBs |
| Typical Gate Count | 5,000 - 6,000 gates | 5,000 - 6,000 gates | 5,000 - 6,000 gates | 6,000 gates | 6,000 gates | 5,000 - 6,000 gates |
| Performance Grade | 100 MHz | 100 MHz | 125 MHz | up to 227 MHz | Speed grade 7 (~150 MHz) | Speed grade 8 (~80 MHz) |
| Technology | 5V CMOS, SRAM-based | 5V CMOS, SRAM-based | 5V CMOS, SRAM-based | 5V CMOS, SRAM-based | 5V CMOS, SRAM-based | 5V CMOS, SRAM-based |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Approx. Unit Price (qty-1) | $46.79 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- XC3000L family member with documented commercial-temperature grade (vs XC3090A-100PC84C)
- Same 320-CLB density as XC3100A drop-ins at lower cost (vs XC3090A-7PC84C)
- Lower-speed -8 grade available for power-sensitive designs (vs XC3090L-125PC84C)
Design Notes
The XC3090LTM-100PC84C operates from a single 5V supply (VCC pins 16 and 70) with GND pins 1 and 43. Decouple each VCC pin with a 0.1uF ceramic capacitor placed within 5 mm of the package pin, and add a single 10uF tantalum or aluminum bulk capacitor near the package. The XC3000 family draws significant inrush current during configuration bitstream loading; ensure the 5V regulator can source the inrush without sagging below 4.75V. For battery-backed applications, hold the device in PROGRAM state during power-down to prevent partial-configuration corruption of the SRAM cells.
The XC3000 family uses SRAM-based configuration that is volatile - the bitstream must be reloaded at every power-up from an external configuration PROM (XC17xx series) or microcontroller. Designers commonly forget that the DONE pin is open-drain and requires an external pull-up to VCC, and that the INIT pin must be monitored to detect configuration errors. After power-up, the I/O pins are tri-stated until configuration completes, which can cause bus contention if external pull-ups or bus-keeper resistors are not provided. Estimated: at 100 MHz and 320 CLBs, the worst-case I/O toggle current can reach 200-300 mA, exceeding the default I/O sink rating of 12 mA per pin.
The 84-pin PLCC footprint has J-lead terminals on a 1.27 mm pitch with the square body measuring approximately 29.4 mm per side. Provide at least 1.5 mm of clearance around the package for socket insertion or rework. Use a PLCC socket (such as 3M 8432-η³»ε or equivalent) during prototyping to allow easy device removal for programming or replacement. For production, hand-soldering is acceptable but reflow profiles must respect the PLCC plastic's 220C peak temperature limit. Ground and VCC traces should be at least 0.5 mm wide and routed directly under the package to provide low-impedance power distribution.
Compliance Information
The XC3090LTM-100PC84C is a legacy Xilinx part from the XC3000 family (introduced circa 1992-1995), predating modern RoHS/REACH compliance requirements. Compliance status depends on the specific factory date code and lot; confirm RoHS and lead-free status with the broker before placing production orders. AEC-Q100 is not applicable for this commercial-grade FPGA.
