Reported by TechPowerUp on 2026-10-09. Summarized and analyzed by XAIPART Editorial.
What happened
At the Linux Plumbers Conference (LPC) 2026 in Prague on , AMD engineer Bharata Bhasker Rao presented the IBS Memory Profiler, a hardware feature of the upcoming Zen 6 processorsS1.
Instruction-Based Sampling (IBS) is AMD's existing profiling hardware, and Zen 6 adds a separate, lighter instance that only samples data memory accessesS1. Each sample delivers the kernel the physical address of the access and indicates whether the data came from DRAM or external memory such as CXLS1. This is relevant on tiered-memory servers, where Linux must locate frequently used ("hot") pages on slower CXL memory and migrate them to DRAMS1. AMD's EPYC 9006 "Venice" chips support memory expansion via CXL 3.1S1.
Linux currently identifies those pages by scanning page tables and trapping page faults, and AMD proposes feeding the profiler's samples into pghot, an in-development kernel subsystem for hot page trackingS1. On a test system with 256 logical CPUs and 256 GB of CXL memory, XSBench ran at 4.57x over a no-tiering baseline versus 1.18x for the current method, and Graph500 hit 3.17x versus 2.34xS1. Redis showed no gain, and NAS BT landed slightly behind; per-folio promotion cost fell from 26.1 to 15.8 microseconds in an overhead test, though that benchmark finished about 5% slowerS1. These are AMD's own figures, the slides list no virtualization support for the profiler, and EPYC Venice is in production with cloud deployments expected later this yearS1.
| Metric | Reported value | Source |
|---|---|---|
| LPC 2026 presentation date | 2026-10-05, Prague | [S1] |
| Test system | 256 logical CPUs, 256 GB CXL memory | [S1] |
| XSBench speedup (pghot vs current) | 4.57x vs 1.18x over no-tiering | [S1] |
| Graph500 speedup (pghot vs current) | 3.17x vs 2.34x | [S1] |
| Per-folio promotion cost | 26.1 to 15.8 microseconds | [S1] |
| Overhead benchmark delta | about 5% slower | [S1] |
| EPYC Venice CXL support | CXL 3.1 | [S1] |
| Virtualization support for profiler | Not disclosed (slides list none) | [S1] |
Background timeline
- - AMD engineer Bharata Bhasker Rao presents the Zen 6 IBS Memory Profiler at LPC 2026 in Prague [S1].
- - TechPowerUp publishes its summary of the LPC talk [S1].
- No prior milestones disclosed by the source.
XAIPART take
Technical impact
The Zen 6 IBS Memory Profiler is a hardware sampler, not an OS feature, so designers evaluating EPYC 9006 "Venice" platforms must treat it as silicon-tied capability: any benefit only appears on Zen 6 parts and depends on a kernel that consumes the samplesS1. The lack of disclosed virtualization support means hypervisor-mediated tiering on AMD EPYC Venice is unlikely to use this path soon, pushing VM workloads back to software-only page scanning or to alternatives such as Intel's MLDOM/2D-style VM memory tagging. XAIPART analysis
Market impact
For procurement, the immediate effect is on CXL 3.1 tiered-memory configurations built around EPYC Venice: buyers should expect first-generation pghot integration to be uneven, since AMD's own numbers show workload-dependent results from a 4.57x XSBench gain down to no gain on RedisS1. Cloud deployments are expected later this year, so lead-time pressure on EPYC 9006 "Venice" parts and CXL 3.1 expansion modules is plausible but not yet quantified by the source. XAIPART analysis
Action
Engineers designing tiered-memory EPYC Venice servers should plan for a mixed-outcome rollout: validate pghot-driven promotion on representative workloads (HPC, key-value, NAS, graph) before committing to large CXL 3.1 memory-expansion purchases, and budget for kernel-side work since the pghot patches are still in developmentS1. Track upstream pghot patch status and confirm with AMD whether virtualization support will arrive in a follow-up silicon or firmware revision. XAIPART analysis
XAIPART Forecast
XAIPART expects that by , if upstream pghot patches for the Zen 6 IBS Memory Profiler are not merged into a Linux kernel release that EPYC Venice cloud deployments can run, the headline 4.57x XSBench gain reported on AMD's 256 logical CPU / 256 GB CXL test system will not translate into broadly available production speedups for tiered-memory cloud servers. XAIPART analysis
Facts are as reported by the cited source. The design-in, sourcing and forward-looking statements above are XAIPART's analysis, not the source's claims. Uncertainty: all benchmark figures are AMD's own, virtualization support is absent from the disclosed slides, and the source gives no timeline for upstream Linux kernel merging of pghot or for AMD disclosing VM-mode operation.
Corrections: none at publication. This brief will be updated with a timestamp if the source corrects its report.
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So wurde dies erstellt
Prozessnachweise – Abruf, Quellenprüfung, Modell und Gate
| Source fetched | TechPowerUp · www.techpowerup.com · 2,834 chars · fetch status success |
|---|---|
| Source sanity (S1) | ok — passed before any model call (no s1_ block recorded) |
| Model / prompt | MiniMax-M3 · prompt Blog Agent - News Summary (v2.8-final) · 6,966 tokens · 21.5s · run completed |
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