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ATM90E36A-AU - 3-Phase Energy Metering AFE, 48-TQFP | Microchip
The Microchip (formerly Atmel) ATM90E36A-AU is a high-performance, poly-phase energy metering analog front-end (AFE) IC designed for three-phase four-wire (3P4W, Y0) and three-phase three-wire (3P3W, Y or Δ) systems, supplied in a 48-pin TQFP (7x7 mm) package. It integrates seven input channels (three voltage, four current) and provides active, reactive, and apparent energy computation with 0.1% accuracy over a wide dynamic range of 1000:1. The device operates from a 3.3V analog/digital supply with 1.8V internal logic support. An energy metering AFE (analog front-end) is a mixed-signal IC that combines sigma-delta ADCs, anti-aliasing filters, a DSP-based measurement engine, and digital calibration blocks. AFEs sit between current transformers / shunt resistors / voltage dividers and a host microcontroller, converting the analog line signals into computed energy quantities, RMS values, THD, and phase angles. Within the broader hierarchy, an energy metering AFE belongs to power management ICs and is typically classified as a data acquisition / signal chain IC in industrial metering subsystems. Key features include a built-in digital signal processor (DSP) for on-chip computation of mean active/reactive/apparent power, RMS voltage and current, power factor, line frequency, and harmonic distortion (THD) up to the 21st order. The IC exposes three configurable CF (calibration frequency) pulse outputs for active/reactive/apparent energy, plus three zero-crossing detection pins (ZX0/ZX1/ZX2) and three interrupt/warning outputs (IRQ0, IRQ1, WarnOut). Communication to the host MCU is via an SPI/UART selectable serial interface at up to 4 Mbps. Architecturally, the ATM90E36A-AU uses simultaneous sampling 16-bit second-order sigma-delta ADCs per channel with integrated digital integrators, eliminating the need for an external analog anti-aliasing filter on each current channel. On-chip temperature compensation and per-phase gain/phase calibration registers allow meter class 0.5S / 1.0 accuracy. The -AU suffix indicates the industrial temperature grade (-40C to +85C). Typical applications include three-phase smart electricity meters, sub-metering in solar PV and energy storage inverters, EV charging station billing, data acquisition terminals, power quality monitors, and industrial three-phase motor energy dashboards. The wide 1000:1 dynamic range also supports both CT-based and Rogowski-coil current sensors. The TQFP-48 footprint suits both through-hole-friendly reflow designs and retrofit metering modules. When designing with this part, pay attention to the SPI/UART mode selection pin and ensure the host MCU firmware matches the configured baud rate or clock polarity; mismatch is the most common bring-up issue. Decouple AVDD/DVDD with low-ESR 10uF plus 100nF ceramic pairs and provide a clean analog ground island to achieve the rated accuracy at low currents. This page synthesizes distributor pricing, drop-in package alternatives, and practical calibration notes not found in the bare manufacturer datasheet, with cross-references verified against the M90E36A datasheet revision and Microchip product family page.
ATMXT112S-MAUR - 112-Node maXTouch Touch Controller | Microchip
The Microchip Technology ATMXT112S-MAUR is a maXTouch S-Series capacitive touchscreen controller IC with 112 mutual-capacitance sensing nodes, housed in a 32-pin UQFN (4x4 mm) package. It supports screens up to 3.5 inches and delivers smartphone-grade multi-touch performance with integrated noise mitigation for operation in noisy environments. A capacitive touch controller is a mixed-signal IC that measures tiny capacitance changes on a touch sensor grid, converts them into touch coordinates, and communicates them to a host processor. In the system hierarchy, a touchscreen controller sits between the touch sensor (ITO pattern on glass or film) and the host MCU or application processor, forming part of the human-machine interface subsystem alongside display drivers and haptic feedback devices. Key features of the ATMXT112S-MAUR include its 112-node sensing matrix for dense electrode layouts, the maXTouch S-Series architecture optimized for small displays up to 3.5 inches, and an advanced noise mitigation system that rejects interference from display drivers and chargers. The device integrates acquisition logic and post-processing, offloading touch detection from the host CPU. Technically, the maXTouch S-Series uses a proprietary acquisition engine with mutual-capacitance scanning and built-in self-calibration. Configuration data is stored on-chip in nonvolatile memory, and communication with the host uses an I2C-compatible interface. The device supports moisture and gloved-finger handling modes and provides robust reporting rates for responsive user interfaces. Typical applications include feature phone touchscreens, handheld game consoles, digital still cameras, portable GPS navigation devices, and small industrial HMI panels. Any battery-powered product with a 3.5-inch or smaller capacitive display benefits from the low-power touch wake-up and high noise immunity. Design consideration: because touch performance depends strongly on the sensor pattern and panel stack-up, use Microchip's maXTouch configuration tooling and reference sensor designs; improper grounding near display VCOM lines is the most common source of false touches. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ATMXT1386-Z2UIR - maXTouch 1386-Node Touch Controller | Microchip
The Microchip Technology ATMXT1386-Z2UIR is a capacitive touch screen controller from the maXTouch product platform, implementing a 1386-node multi-chip solution (4 chips) that combines charge-transfer acquisition technology with a powerful 32-bit AVR microcontroller core. It is supplied in a 64-terminal HVQCCN (LCC64) surface-mount package. A capacitive touch controller is an interface IC that measures changes in capacitance across a touch sensor grid, converts those measurements into touch coordinates, and communicates them to a host processor. Within the semiconductor hierarchy it sits under data acquisition ICs, specifically touch screen converters and controllers, and forms part of the broader human-machine interface (HMI) signal chain that includes the sensor glass, the controller IC, and the host firmware. Key differentiating features include the 1386-node acquisition capacity, which supports large-format touch panels with many simultaneous sensing channels; the multi-chip architecture that lets four devices cooperate on a single panel; and the integrated 32-bit AVR processing that performs filtering and gesture detection on-chip, reducing host CPU load. The maXTouch platform firmware can be updated in-system, enabling tuning for different glass stack-ups. The charge-transfer acquisition technique offers strong signal-to-noise performance against display noise, which is important for designs where the touch sensor is integrated into or placed close to an LCD. On-chip AVR computation allows advanced touch features such as multi-touch tracking, palm rejection, and moisture compensation depending on the configured firmware. Typical applications include industrial HMI touch panels, large-format touch screens for appliances and kiosks, medical equipment control surfaces, and embedded systems requiring robust multi-touch input on medium-to-large sensor arrays. A key design consideration is that this device has been discontinued by Microchip; the manufacturer officially recommends the ATMXT1066T2 touch controller as the alternative for new designs, so availability should be confirmed before committing to a BOM. This page synthesizes distributor listings, manufacturer product-page data, and cross-reference findings, including drop-in-replacement guidance and procurement notes not found in the manufacturer datasheet.
ATMXT1386E-Z2U - maXTouch 1386-Node Touch Controller | Microchip
The Microchip Technology ATMXT1386E-Z2U is a capacitive touchscreen controller from the maXTouch product platform, implementing a 1386-node multi-chip solution built from four chips. It combines Atmel's patented QMatrix charge-transfer capacitive sensing method with a powerful 32-bit AVR microcontroller, and supports up to 16 simultaneous touches with fast response time. A capacitive touchscreen controller is a type of sensor interface IC that measures mutual capacitance changes across a touch sensor grid, classifies and tracks finger touches, and reports coordinates to a host processor. Within the system hierarchy, it sits in the signal chain between the touch sensor (a patterned ITO or similar electrode layer on the display) and the host MCU or application processor, forming part of the broader human-machine interface (HMI) subsystem. Key features include the 1386 mutual-capacitance node count, which suits medium-to-large touch panels; the patented charge-transfer acquisition engine, which delivers high signal-to-noise measurement accuracy; and multi-touch tracking of up to 16 touches. The high-performance architecture enables fast response and unlimited-touch reporting up to the 16-touch limit, making the device suitable for demanding interactive displays. Technically, the mXT1386E uses a unique charge-transfer acquisition engine implementing the QMatrix capacitive sensing method patented by Atmel. Coupled with a state-of-the-art 32-bit AVR CPU, the entire touchscreen sensing solution can measure, classify and track finger touches with a high degree of accuracy. As a multi-chip (4-chip) solution, the family coordinates sensing across the node array within one firmware-managed platform. Typical applications include tablet and e-reader touchscreens, industrial HMI panels, and consumer electronics displays requiring robust multi-touch performance with gloved-hand and noise immunity characteristic of the maXTouch platform. Design consideration: this part is a multi-chip solution, so verify board space, mechanical stacking and firmware/configuration compatibility against the replacement controller before redesign. Note that Microchip has officially recommended the ATMXT1066T2 as the alternative touch controller for this family. This page synthesizes distributor sourcing data, the manufacturer-recommended replacement, and practical design notes not found in the manufacturer datasheet.
ATMXT1386E-Z2UR - maXTouch 1386-Node Touch Controller | Microchip
The Microchip Technology ATMXT1386E-Z2UR is a 1386-node capacitive touch screen controller from the maXTouch product platform, implemented as a multi-chip solution combining four chips that pair charge-transfer acquisition technology with a powerful 32-bit AVR microcontroller core. It supports up to 16 simultaneous touches with fast response, and communicates with the host processor through either an I2C-compatible interface or a USB interface, though only one interface should be used in any single design. A capacitive touch controller is an interface IC that measures changes in capacitance across a touch sensor grid, applies touch-detection and noise-immunity algorithms, and reports touch coordinates to a host MCU or application processor. Within the semiconductor hierarchy it sits under touch screen controllers, a subcategory of sensor interface ICs in the maXTouch family spanning small single-chip solutions up to large multi-chip nodes for large-format touch panels. Key differentiating features include the very high 1386-node sensor channel count, support for up to 16 concurrent touch points, self- and mutual-capacitance charge-transfer acquisition, and dual host communication options (I2C-compatible or USB). The multi-chip architecture scales acquisition bandwidth for large touch panels used in industrial HMI and commercial display designs. Technically, the ATMXT1386E integrates four chips operating as one synchronized controller, with the 32-bit AVR execution core running Microchip's maXTouch firmware for touch detection, palm rejection, and noise filtering. Configuration is typically loaded into EEPROM/flash by the host at power-up, allowing tuning of sensitivity and gesture behavior without firmware changes. Typical applications include large-format industrial touch monitors, commercial kiosks and point-of-information terminals, and multi-touch human-machine interfaces where many sensor nodes and reliable multi-touch detection are required. A key design consideration is that Microchip has flagged this product for end-of-life: the manufacturer-recommended alternative touch controller is the ATMXT1066T2, so new designs should target that device while the ATMXT1386E family remains available for last-time-buy and service inventory. This page synthesizes distributor sourcing, the manufacturer-recommended successor, and practical design guidance not found in the standard datasheet listing.
ATMXT1386XES-CHPSET2 - 1386-Node maXTouch Touch IC | Microchip
The Microchip Technology ATMXT1386XES-CHPSET2 is a 1386-node capacitive touch screen sensor IC solution from the maXTouch product platform, supplied as a multi-chip set of 4 chips. By combining charge-transfer touch sensing technology with a powerful 32-bit AVR microcontroller core, this device delivers large-format projected-capacitive touch detection with Microchip's maXTouch signal-processing algorithms. A capacitive touch controller is a specialized mixed-signal IC that scans a matrix of mutual-capacitance nodes on a touch sensor panel, converts capacitance changes into digital coordinates, and reports touch positions to a host processor over a digital interface. In the product taxonomy, this device belongs to Interface ICs > capacitive touch sensors, which sits within the broader families of human-interface devices, sensor interfaces, and mixed-signal integrated circuits. Key characteristics of the ATMXT1386 family include the 1386-node sensing capacity, an on-chip 32-bit AVR processing core for autonomous touch acquisition, and maXTouch filtering that supports gloved operation, passive stylus, and water-rejection behavior typical of the platform. The XES-CHPSET2 ordering code denotes a chip-set (multi-chip) configuration rather than a single monolithic die, which system designers must account for in PCB partitioning. Technically, the charge-transfer acquisition engine periodically drives and senses the electrode matrix, while the embedded AVR firmware applies noise filtering, baseline tracking, and touch classification. This architecture offloads all touch processing from the host, requiring only configuration data and touch reports over the communication interface. Typical applications include large-format touchscreen displays for industrial human-machine interfaces (HMI), point-of-information kiosks, and other commercial touch systems that previously used this high-node-count controller. A key design consideration: Microchip lists the ATMXT1066T2 as the recommended alternative touch controller for the ATMXT1386, since this multi-chip solution is obsolete and no longer recommended for new designs. This page synthesizes distributor availability data, the manufacturer's recommended migration path, and drop-in alternative analysis not found on the Microchip product page alone.
ATMXT1664S1-CU - maXTouch Touchscreen Controller IC | Microchip Technology
The Microchip Technology ATMXT1664S1-CU is a maXTouch capacitive touchscreen controller IC from the maXTouch S-series family, supporting 1664 mutual-capacitance sensing nodes for projected-capacitive touch screens, supplied in a compact surface-mount package with RoHS3-compliant construction. According to distributor listings including DigiKey and Octopart, the device is classified as a Touch Screen Controller (IC SENSOR MAXTOUCH). A capacitive touchscreen controller measures mutual capacitance across a matrix of transmit and receive electrodes on the touch sensor. When a finger or passive stylus approaches the intersection of electrodes, local capacitance changes; the controller scans the matrix, converts the capacitance deltas to touch coordinates, applies gesture and noise filtering, and reports touch data to a host processor over an interface such as I2C or SPI. Touchscreen controllers sit within the broader hierarchy of sensor interface ICs and human-machine interface (HMI) semiconductors. The maXTouch S-series architecture integrates a high-performance acquisition engine with differential charge amplifiers, a configurable scan sequencer, and an embedded MCU core executing Microchip-supplied object-based firmware. Self- and mutual-capacitance fusion enables gloved-hand operation and water rejection, while frequency-hopping acquisition combats charger and display noise - a critical requirement for thin bezel tablets, POS terminals, and automotive HMI panels. Technical strengths of the family include high node counts supporting large-format touch panels, the maXTouch object model allowing configuration of key timings and thresholds via I2C registers, and mature firmware tooling through Microchip's maXTouch studio ecosystem. The S1 model designation reflects the firmware/feature configuration of the 1664-node silicon. Typical applications include 7-inch to 13-inch capacitive touchscreens in tablets, human-machine interfaces for white goods and appliances, point-of-sale and ticketing terminals, smart-home wall panels, and industrial operator panels where multi-touch and robust noise immunity are required. When designing with this controller, allocate a clean low-noise analog supply for the sensing core and route the sensor flex connector away from switching regulators; charger-mode noise often dominates real-world touch performance and must be verified with the intended display and charger pair. This page synthesizes distributor sourcing data, drop-in family alternatives, and practical design notes not found in the manufacturer datasheet, with pricing as of 2026-09-19.
ATMXT1664S1-CUR - maXTouch 1664-Channel Touch Controller | Microchip
The Microchip Technology ATMXT1664S1-CUR is a maXTouch S Series capacitive touchscreen controller with 1664 mutual-sense channels, built on a 32-bit AVR microcontroller architecture, supplied in a reflow-capable surface-mount package for large-format touchscreen devices. A capacitive touch screen controller is an interface IC that measures capacitance changes across a grid of sensor electrodes to detect finger and stylus positions. Within the system hierarchy, it sits between the raw touch sensor (ITO pattern on glass or film) and the host application processor, converting analog charge-transfer measurements into touch coordinates over a digital interface. The maXTouch family from Microchip (originally Atmel) is a widely adopted line of such controllers used from wearables to large interactive displays. The ATMXT1664S1 belongs to the S Series, which brings the maXTouch architecture to large touchscreen devices. Its 1664 sensing channels support high electrode counts typical of large-format panels, while the integrated 32-bit AVR core performs on-chip acquisition, filtering, and gesture processing, offloading the host processor. Multiple S Series devices can operate simultaneously to drive very large screens, a scalability feature documented by Microchip for this family. The suffix structure of the part number encodes ordering options such as temperature grade and packaging (-CUR indicates a reflow-eligible, RoHS-grade ordering variant per Microchip nomenclature). As with all maXTouch parts, configuration of sensitivity, report rate, and multi-touch behavior is performed via firmware objects downloaded to the controller, allowing one PCB design to be tuned for different sensor stacks. Typical applications include large interactive displays, industrial HMI panels, point-of-information kiosks, and premium consumer touch devices where high channel count and robust noise immunity near displays or chargers are required. A key design consideration is that maXTouch controllers require a configuration file matched to the specific sensor pattern and stack-up; mismatched configurations degrade linearity and report rate. Verify communication with the host over the I2C-compatible interface during bring-up. This page synthesizes distributor availability, Microchip product data, and the manufacturer-recommended replacement ATMXT1664T3 into one reference, adding drop-in alternative guidance and design notes not found in the datasheet alone.
ATMXT2952T2-C2U - maXTouch Touch Controller | Microchip
The Microchip Technology ATMXT2952T2-C2U is a maXTouch capacitive touchscreen controller IC from the mXT2952T2 family, supporting up to 2952 touch channels and display sizes up to 21 inches, aimed primarily at industrial designs and housed in a BGA package. A capacitive touchscreen controller is a mixed-signal IC that measures mutual-capacitance changes across a touch sensor grid, converts the raw charge-transfer measurements into touch coordinates and gesture information, and reports them to a host processor over a digital interface. In the system hierarchy, it sits within the human-interface / data acquisition domain: touchscreen controller -> capacitive touch sensor IC -> sensor interface IC -> mixed-signal semiconductor. Key features of the ATMXT2952T2 family include Microchip's Adaptive Sensing technology, which automatically and intelligently switches between touch operating modes based on the detected object or environment, dynamic touch classification for finger, glove, stylus, and water rejection scenarios, and a debug port for tuning (per Microchip application note QTAN0050 'Using the maXTouch Debug Port'). The device supports I2C host communication; in I2C mode the pull-up resistor on the DBG_SS/GPIO0 shared ball is optional and present only if the ball is used as DBG_SS. The architecture pairs a charge-transfer analog front end with on-chip processing that performs self- and mutual-capacitance scanning, noise filtering, and touch classification. Adaptive Sensing allows the same controller to deliver reliable touch performance on thick cover lenses, in wet conditions, and under EMI conditions typical of industrial panels. Typical applications include industrial HMI touch panels up to 21 inches, factory automation displays, medical equipment screens, and commercial kiosk or point-of-information terminals where gloved-hand and water rejection are required. A key design consideration is the shared DBG_SS/GPIO0 ball: only one of these two functions can be selected, and the circuit must be designed accordingly; consult the manufacturer datasheet and QTAN0050 before finalizing the sensor flex pin mapping. Note that Microchip identifies ATMXT2952TD as the recommended alternative touch controller for the ATMXT2952T2, which is relevant for new designs and long-term supply planning. This page synthesizes distributor availability, the recommended replacement, and design guidance not consolidated in the manufacturer datasheet.
ATMXT768E-ABR - maXTouch Touchscreen Controller | Microchip
The Microchip Technology ATMXT768E-ABR is a maXTouch mXT768E-AT mutual-capacitance touchscreen controller IC designed for projected-capacitive touchscreens of up to 10.1-inch diagonal or even larger. It belongs to Microchip's maXTouch family of capacitive touch controllers and integrates signal-acquisition, touch-decision, and host-interface functions in a single device. A projected-capacitive (PCAP) touchscreen controller is a specialized mixed-signal IC that drives excitation signals across rows and columns of a transparent ITO sensor grid and measures mutual capacitance changes at each intersection. Within the system hierarchy, it sits between the raw touch sensor laminate and the host processor, delivering pre-processed touch coordinates over a digital interface. This class of device is fundamental to modern human-machine interface (HMI) design in industrial, medical, and consumer equipment. Key characteristics of the mXT768E-AT include high responsiveness for large-format screens, support for multi-touch reporting, and Microchip's maXTouch object-based reporting architecture in which touch data is conveyed as structured objects over an I2C or SPI-compatible host interface. The device is firmware-configurable, allowing tuning of sensitivity, rejection thresholds, and gesture behavior to match specific sensor stacks. The ATMXT768E-ABR was originally targeted at tablets, industrial HMI panels, point-of-sale terminals, and medical monitors in the 7-inch to 10.1-inch class. Note that Microchip's product page indicates this part is no longer recommended for new designs and recommends the ATMXT1189TD-A as the alternative touch controller for new development. Design consideration: because the mXT768E-AT is in end-of-life transition, new designs should evaluate the ATMXT1189TD-A and verify firmware migration effort, sensor-stack compatibility, and pin mapping before committing to a layout. This page synthesizes distributor availability, cross-reference data, lifecycle status, and practical design notes not found in the manufacturer datasheet alone, helping engineers make a supply-risk-aware selection decision.
ATMXTS100-CU - maXStylus Active Stylus ASIC | Microchip
The Microchip Technology ATMXTS100-CU is a maXStylus Gen I active stylus ASIC designed for capacitive touch sensing systems, classified under Interface - Sensor, Capacitive Touch ICs and belonging to the maXTouch product series from Microchip Technology. The device ships in tape-and-reel packaging with a standard package quantity of 6,000 units per reel, and the part status is listed as Active per distributor and manufacturer data. An active stylus controller IC is a specialized mixed-signal device that implements the transmit and signal-processing functions of an active pen system, enabling a battery-powered stylus to communicate position, pressure, and hover information with a capacitive touchscreen that is driven by a companion maXTouch touch controller. Within the system hierarchy, this device sits alongside touch sensors and touch screen controllers inside the human-interface input subsystem of tablets, e-readers, signature pads, and other pen-enabled displays. Key characteristics identified from verified distributor data include the maXStylus Gen I generation designation, maXTouch series membership, capacitive touch interface classification, and active lifecycle status. This positions the ATMXTS100-CU within Microchip's established maXTouch ecosystem, which is widely deployed in commercial and industrial touchscreen designs. Architecturally, active stylus ASICs coordinate the stylus-tip signal generation and timing with the host touchscreen controller so that palm rejection, hover detection, and fine-line pen input can be achieved on standard mutual-capacitance panels. Designers typically pair the stylus ASIC with a maXTouch touchscreen controller on the host side to form a complete pen-and-touch subsystem. Typical applications include active pen input for tablets and 2-in-1 computing devices, digital signature capture terminals, and industrial touch panels requiring stylus precision. In each case the ASIC provides the dedicated stylus-side signal chain that a general-purpose MCU would struggle to replicate with equivalent latency and power efficiency. A key design consideration is that per available cross-reference information this device is generally not pin-compatible with capacitive touch sensors from competing vendors, so second-sourcing requires careful I/O voltage and interface evaluation. This page synthesizes distributor pricing channels, verified lifecycle data, and practical design notes not consolidated in the manufacturer datasheet.
ATPL230A-AKU-R - PRIME PLC Modem 128.6Kbps | Microchip
The Microchip Technology ATPL230A-AKU-R is a PRIME-compliant power line communications (PLC) base band modem IC delivering data rates up to 128.6 kbps from a 3.3 V supply in an 80-pin LQFP (12x12 mm) package. It integrates an AES-128 crypto engine, operates from -40C to +85C, and supports CENELEC-A, FCC, and ARIB frequency bands. A power line communications modem is a specialized embedded device that transmits data over existing AC mains or DC power distribution wiring, eliminating the need for dedicated communication cabling. In the system hierarchy, the ATPL230A belongs to the class of application-specific microcontrollers and communication transceivers, bridging the gap between a host MCU and the physical power-line medium via an analog front end and coupling network. Key features include full compliance with the PHY layer of the PRIME (PRoducts for Intelligent Metering Evolution) specification v1.3 and v1.4, independently selectable transmission bands up to 472 kHz, and baud rates ranging from 5.4 kbps to 128.6 kbps. Additional robust modes and frequency band extension improve link reliability in noisy grid environments, while the hardware AES-128 engine secures metering data without burdening the host processor. The ATPL230A uses a flexible architecture composed of hardware accelerators and co-processors, enabling a highly efficient PRIME PHY implementation. An SPI interface connects the modem to an external host microcontroller, which handles PRIME MAC/CON layers and application logic. This partitioning allows firmware upgrades on the host without touching the certified PHY layer. Typical applications include smart metering (electricity, gas, water), smart grid street lighting control, solar inverter communication, and building automation over mains wiring. The industrial temperature grade of -40C to +85C supports outdoor and cabinet-mounted metering equipment. When designing with this device, budget the analog front end (line driver, coupling transformer, and filters) carefully, as PHY performance in CENELEC-A, FCC, and ARIB bands depends strongly on the external network; Microchip reference designs should be followed for coupling circuitry. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
ATPL250A-AKU-R - G3-PLC Power Line Modem IC | Microchip
The Microchip Technology ATPL250A-AKU-R is a G3-PLC (Power Line Communication) modem system-on-chip delivered in an 80-pin LQFP (AKU) surface-mount package, rated for the industrial temperature range of -40C to +85C and supplied in Tape & Reel (T&R) green/RoHS packaging. It integrates hardware accelerators and coprocessors that achieve a highly efficient G3 PHY layer implementation for narrowband power line communication. A power line communication modem is a communication IC that transmits data over existing AC mains or DC power lines by modulating a carrier signal onto the line, eliminating the need for dedicated wiring. Within the system hierarchy, the ATPL250A sits between the physical analog line front end and the host microcontroller, offloading the computationally demanding PHY and MAC layers of the G3-PLC standard from the application processor. G3-PLC is an open standard promoted by the G3-PLC Alliance and supported by internationally recognized standards bodies, making it the dominant PLC technology for smart grid infrastructure. Key features include flexible support for G3-PLC CENELEC, ARIB, and FCC frequency profiles, which allows one design to serve global markets with different regulatory band plans. The hardware-accelerated architecture handles OFDM modulation, forward error correction, and convolutional interleaving in dedicated logic, delivering deterministic real-time performance that a pure software implementation cannot match. The device is classified by distributors as a Network Controller & Processor IC / power line communications microcontroller. The ATPL250A implements the G3 PHY layer with hardware accelerators and coprocessors, achieving spectral efficiency and robustness over hostile power line channels characterized by multipath fading, impulsive noise, and frequency-selective attenuation. This architecture lets a companion host MCU manage application logic, metering computation, or protocol translation while the ATPL250A transparently maintains the PLC link, including adaptive tone mapping and channel estimation. Typical applications include smart metering (electricity meters and data concentrators), smart lighting control, industrial and home automation, and home energy management gateways. In a data concentrator, the ATPL250A aggregates PLC traffic from hundreds of meters onto a backhaul link, making its PHY efficiency directly responsible for network capacity. When designing with the ATPL250A, pay close attention to the analog line driver and coupling network: PCB layout of the transmit path and use of the reference design from the Atmel/Microchip user manual are critical to meeting G3-PLC Alliance interoperability and local emissions regulations. This page synthesizes verified distributor data, drop-in alternatives from the same LQFP-80 ATPL PLC family, and selection guidance not consolidated in the manufacturer datasheet. Pricing and availability were last verified on 2026-09-19.
ATPL250A-AKU-Y - G3-PLC Power Line Modem 3.3V | Microchip
The Microchip Technology ATPL250A-AKU-Y is a G3-PLC (Power Line Communication) modem microcontroller IC operating from a 3.3V supply, housed in an 80-pin LQFP (AKU) package, rated for the industrial temperature range of -40C to +85C. A power line communication modem is a specialized communication IC that transmits and receives data over existing AC mains or DC power lines, eliminating the need for dedicated wiring. It sits within the broader hierarchy of communication ICs and embedded processors: PLC modem -> telecom interface IC -> network controller -> microcontroller-class system-on-chip. G3-PLC is an open standard promoted by the G3-PLC Alliance and supported by internationally recognized standards bodies, widely deployed in smart grid infrastructure. The ATPL250A features a flexible architecture composed of hardware accelerators and coprocessors that achieve a very efficient G3 PHY layer implementation. According to the Microchip ATPL250A datasheet, the device supports G3-PLC CENELEC, ARIB, and FCC profiles, making it adaptable to regional regulatory band plans across Europe, Japan, and North America. The hardware-based PHY offloads modulation, coding, and windowing tasks from software, reducing CPU load and improving real-time determinism. This combination of flexible coprocessor architecture and multi-profile band support makes the ATPL250A a compact and highly efficient device for a wide range of smart grid applications, including smart metering (smart meters and data concentrators), street lighting control, industrial and home automation, and home area network gateways. The 80-pin LQFP provides sufficient GPIO and peripheral interfaces to host application firmware alongside the modem function. When designing with the ATPL250A, careful attention must be paid to the analog front-end coupling network between the modem and the power line, as line impedance variation directly affects achievable data rate and link reliability. Microchip provides the ATPL250A Evaluation Kit (documented in device document 00002299B) as a hardware platform for evaluating the modem and integrating it into custom designs. This page synthesizes distributor pricing, drop-in family alternatives, and practical design guidance not found in the manufacturer datasheet, consolidating data from DigiKey, Mouser, Octopart, and Microchip documentation as of 2026-09-19.
AX58100LT - 2/3-Port EtherCAT Slave Controller | ASIX
The ASIX Electronics AX58100LT is a 2/3-port EtherCAT Slave Controller (ESC) with two integrated Fast Ethernet PHYs, operating from a 3.3V supply and packaged in an 80-pin LQFP-EP (10x10 mm). It implements the EtherCAT slave protocol in hardware and exposes 2 or 3 PHY ports plus digital host interfaces (SPI / host bus) to an external MCU, making it one of the most integrated single-chip ESCs in its class. An EtherCAT Slave Controller is a specialized industrial Ethernet IC that handles the EtherCAT protocol (a deterministic real-time Ethernet standard originally developed by Beckhoff and standardized by the EtherCAT Technology Group) without burdening the host CPU. The EtherCAT protocol itself falls under the broader hierarchy of industrial fieldbuses -> real-time Ethernet -> industrial communication IC -> semiconductor. The "slave" role means the device sits on the bus as a node that processes the EtherCAT datagram on the fly as it traverses each port, in contrast to an EtherCAT master which orchestrates the network. The AX58100LT integrates two 100BASE-TX Fast Ethernet PHYs directly on-die, eliminating the need for external PHY chips and reducing BOM cost, PCB area, and signal-integrity complexity for servo drives, distributed I/O, and sensor modules. With 100 Mbit/s full-duplex ports, it supports standard EtherCAT cycle times down to the 12.5 us micro-period range and the typical 1 ms motion-bus update rate. The industrial-grade -40C to +105C operating range suits it for servo, motion control, and factory automation deployments. Typical applications include EtherCAT servo motor drives, decentralized digital I/O modules, EtherCAT sensor interfaces, robotic joint controllers, EtherCAT junction or branch modules, and other industrial-automation nodes. The STM32F303RE host reference design published by ST validates AX58100LT for FOC (field-oriented control) servo loops and points designers toward proven firmware stacks. When designing with the AX58100LT, ensure the 80-pin LQFP-EP exposed pad is soldered with sufficient thermal via arrays to dissipate internal PHY power, and route the differential MDI pairs as 100-ohm differential controlled-impedance traces. The host MCU should run an ASIX-supported EtherCAT slave stack (e.g., SOES or SSC ported to the chosen MCU) to maximize bus conformance. This page synthesizes distributor pricing, LQFP-80 drop-in alternatives, and practical industrial-board design notes not found in the raw manufacturer datasheet, giving the BOM engineer a complete procurement and design entry point for EtherCAT nodes built around the AX58100LT.
B50280C1KFBG - Octal 10/100/1000 PHY Transceiver | Broadcom
The Broadcom B50280C1KFBG is an octal 10/100/1000 Mbps Ethernet PHY transceiver integrated circuit designed for high-density networking line cards and switch aggregation. The device integrates eight independent Gigabit Ethernet physical layer transceivers in a single package, supporting full-duplex operation over twisted-pair copper media, and is targeted at enterprise switching platforms where port density and per-port power are both critical design constraints. An Ethernet PHY (Physical Layer Device) is the lowest-speed layer of the OSI networking stack, handling the analog signaling, encoding/decoding, clock recovery, and link training required to push bits over a Cat5e/Cat6 cable. PHY transceivers sit beneath the MAC and switch fabric; an octal PHY like the B50280C1KFBG aggregates eight Gigabit PHYs into one IC to simplify PCB routing, reduce component count, and minimize board area compared to using eight discrete single-port PHYs. PHY -> Ethernet transceiver -> Networking IC -> Interface IC -> Integrated Circuit is the broader hypernym chain. The B50280C1KFBG supports auto-negotiation, auto-MDI/MDIX crossover, Energy Efficient Ethernet (EEE, IEEE 802.3az), and 802.1AE MACsec readiness depending on firmware build. Each port independently negotiates 10/100/1000BASE-T, recovers clock and data, and presents GMII/RGMII to the host MAC. The integrated DSP-based echo canceller and baseline wander correction enable robust 100m Cat5e link performance without external magnetics beyond the standard 1:1 transformer. Typical applications include top-of-rack and leaf switches, network interface cards with multi-port PHYs, router line cards, industrial Ethernet switches, and telecom access equipment. Per-port power below ~1W and the octal integration make it especially suited for chassis switches where hundreds of Gigabit ports must be supported within thermal and power budgets. Designers should pay attention to the SGMII/SerDes reference clock architecture, the quad-port group power sequencing, and the requirement for dedicated 1:1 isolation transformers per port. PCB layout for the B50280C1KFBG demands careful 100-ohm differential pair routing for each of the eight MDI channels with strict length matching. This page synthesizes distributor pricing, package specifications, and drop-in alternatives that are not found in the manufacturer datasheet alone, providing a single reference for engineers evaluating the B50280C1KFBG against multi-port PHY options from Broadcom and competitor families.
BCM53158XMB0KFBG - 8-Port GbE Managed Switch SoC | Broadcom
The Broadcom BCM53158XMB0KFBG is an 8-port Gigabit Ethernet managed switch system-on-chip (SoC) integrating 10/100/1000 Base-T/TX PHYs, a high-performance switch fabric, and management interfaces (I2C, SPI) in a single IC. It targets cost-sensitive enterprise, SMB, and industrial Ethernet switching applications, providing Layer 2 switching with full wire-speed performance on all eight integrated PHYs simultaneously. What is a managed Ethernet switch SoC? A managed Ethernet switch SoC combines the physical layer transceivers (PHYs), the Layer-2 packet switch fabric, the lookup table / forwarding engine, and management CPU interfaces into a single silicon die. In the broader system hierarchy it belongs to: Ethernet controller -> network controller -> networking IC -> semiconductor. Unlike a dumb unmanaged switch ASIC or a discrete MAC+external PHY approach, an integrated switch SoC eliminates inter-IC MII/GMII buses, reduces BOM cost, simplifies PCB layout, and shrinks the overall switch design footprint. Key features include eight integrated 10/100/1000 Mbps copper transceivers compliant with IEEE 802.3, 10/100/1000 Base-T/TX standards, wire-speed Layer-2 forwarding, support for advanced QoS, VLAN tagging, IGMP snooping, and port-mirroring features, plus an SPI master/slave port and I2C management interface for CPU-less or host-managed configurations. The integrated PHYs support auto-negotiation, auto-MDI/MDIX crossover, and Energy-Efficient Ethernet (EEE) per IEEE 802.3az. The BCM53158XMB0KFBG uses Broadcom's proven RoboSwitch architecture with shared-memory packet processing and a 12 Gbps internal fabric that supports full line-rate operation on all eight ports. On-chip regulators simplify power-supply sequencing, and per-port activity LEDs are driven directly, removing external LED drivers. Typical applications include 8-port unmanaged/managed Gigabit Ethernet switches, SMB and home-office gateway routers with integrated switching, IP surveillance NVR switches, industrial Ethernet switches, and PoE midspan/spans that need integrated PHY+MAC functionality. When designing with this device, ensure the MII/RGMII/SPI/I2C connections to the host CPU or EEPROM are properly terminated, and that adequate bulk decoupling is placed near the analog supply pins to meet IEEE 802.3 return-loss specifications. The BCM53158XMB0KFBG uses a standard Broadcom switch reference design footprint, simplifying layout reuse across the BCM5315x family. This page synthesizes distributor pricing, drop-in alternatives within the BCM5315x family, and practical design notes not found in the manufacturer datasheet.
BCM53158XMB1KFBG - 12-Port GbE Switch with 10G Uplinks | Broadcom
The Broadcom BCM53158XMB1KFBG is an ultra-low-power 12-port Layer-2 Gigabit Ethernet switch from the RoboSwitch family, integrating 8x Gigabit Ethernet (GE) PHYs, 1x QSGMII, and 2x 10G uplink interfaces in a single 311-pin LFBGA package. According to Broadcom's product family datasheet, the BCM53154/BCM53156/BCM53158 family targets cost-effective low-power applications across SMB, Enterprise, Service-Provider, SOHO, and Industrial markets, with C-Temp commercial operating range. A Layer-2 Ethernet switch is a network device that operates at the data link layer (OSI Layer 2) to forward Ethernet frames between connected devices using MAC address lookup tables. Layer-2 switches form the foundational building blocks of virtually every wired enterprise, industrial, and SMB network. The BCM53158 belongs to the broader taxonomy: Ethernet switch -> network switch -> networking IC -> semiconductor, integrating PHY, MAC, and switch fabric functions on a single die to reduce BOM cost and PCB area. Key features include IEEE 802.3 compliance, support for 10/100/1000 Base-T/TX PHY interfaces, integrated ARM-class management CPU, and a rich set of host interfaces including GPIO, I2C, MII, and SPI. The 10G uplink ports enable aggregation to backbone switches, while the QSGMII provides a quad-SERDES interface commonly used to connect to a host CPU or upstream device. The architecture supports advanced Layer-2 features such as VLAN tagging (802.1Q), QoS prioritization, IGMP snooping, and port-based security. Technical depth: The BCM53158XMB1KFBG implements Broadcom's proven RoboSwitch architecture with shared-memory packet buffer architecture, hardware-based address learning, and store-and-forward switching. The integrated 10G SERDES lanes enable direct connection to SFP+ cages or backplane interfaces without external PHYs. The device typically operates from a single 1.0V/1.2V core supply with 3.3V I/O, and supports Energy Efficient Ethernet (EEE, 802.3az) for power savings on idle links. Typical applications include SMB managed switches, industrial Ethernet switches, SOHO routers with multi-port LAN, service-provider customer-premises equipment (CPE), and enterprise branch office access switches. The 10G uplinks make the device suitable for aggregation tiers where 1G access ports need to feed 10G backbone capacity. Design consideration: When designing with the BCM53158XMB1KFBG, ensure the 311-pin LFBGA PCB land pattern is manufactured with HDI (high-density interconnect) processes such as laser-drilled microvias. Thermal management requires a copper pour beneath the exposed die paddle; without proper thermal vias the device will throttle at high ambient temperatures. Reference Broadcom's reference design guide for magnetics selection and layout. This page synthesizes distributor pricing, parametric comparison with alternative Ethernet switches, application guidance, and design notes not found in the manufacturer datasheet alone - enabling faster design-in and procurement decisions.
BCM53158XUB1KFBG - 8-Port GE Robo2 Switch + 2x10GE Uplinks | Broadcom
The Broadcom BCM53158XUB1KFBG is an 8-port Gigabit Ethernet Layer-2 switch with two 10-Gigabit uplink ports, optimized for ultra-low-power applications in cost-sensitive networking equipment. Part of the BCM53154/BCM53156/BCM53158 family (Robo2 generation), it integrates eight 10/100/1000 BASE-T/TX PHYs, two 10GE SGMII/XFI uplink interfaces, an ARM-based management CPU, packet processors, and MAC address tables, all in a single high-integration BGA package. The 'U' suffix denotes the Commercial grade, and 'B1' identifies the silicon revision. An Ethernet switch IC is a semiconductor device that interconnects several LAN segments at Layer 2 of the OSI model, forwarding Ethernet frames between ports using MAC address lookup tables. Modern highly-integrated switch ICs combine the PHYs, MACs, queueing engines, and CPU subsystem onto a single die, reducing BOM cost and PCB area for routers, gateways, and industrial Ethernet equipment. Within the taxonomy: Ethernet switch -> Layer-2 switch -> network IC -> wired networking semiconductor -> integrated circuit. Key features include support for 8 GE downlink ports plus 2x10GE (or 2x5GE/2x2.5GE) flexible uplinks, IEEE 802.3az Energy-Efficient Ethernet, IPv4/IPv6 L2/L3/L4 ACL, QoS with eight queues per port, and integrated 8051-compatible management. It supports SPI, I2C, MII/GMII, and GPIO host interfaces for management, plus LED controllers for per-port link/activity indication. The device operates from a single 1.0V core supply with integrated voltage regulators, minimizing external component count. The BCM53158XUB1KFBG is fabricated in a low-power CMOS process and uses power-gating on inactive PHYs to deliver sub-watt idle consumption. Its packet processor supports wire-speed forwarding on all GE ports plus line-rate 10GE uplinks, with hardware NAT and tunnel offload for gateway deployments. Built-in TCAM enables wire-speed ACL and QoS classification without CPU intervention. Typical applications include SMB/SOHO routers, enterprise edge switches, xDSL/cable gateways, Wi-Fi 6/7 access points, industrial Ethernet switches, and small-cell backhaul. The 2x10GE uplinks enable aggregation into 10G core networks without an additional switch device. Design considerations include proper decoupling of the 1.0V core rail and thermal management of the high-ball-count BGA package in confined enclosures. This page synthesizes distributor pricing snapshots, package diagrams, and design notes that complement the manufacturer datasheet for engineers evaluating the BCM53158XUB1KFBG.
BCM56524B0KFSBG - 24-Port 108 Gbps Switch Fabric | Broadcom
The Broadcom BCM56524B0KFSBG is a 24-port Gigabit Ethernet switch fabric IC delivering 108 Gbps of aggregate switching bandwidth in a single integrated device, supplied in a BG (ball-grid) package intended for high-density enterprise and SMB switching platforms. It combines PHY-less GbE MACs, a shared-memory packet buffer, and an embedded management CPU to deliver wire-speed switching for layer-2 and basic layer-3 enterprise workloads. An Ethernet switch fabric (also called a switch ASIC or switching chipset) is the silicon heart of a managed network switch that moves packets between physical Ethernet ports and uplinks at line rate. Within the broader hierarchy of networking semiconductors (Ethernet switch -> switch fabric -> communication IC -> semiconductor), the BCM56524B0KFSBG sits in the SME/SMB access-switch tier where cost, integration, and feature density matter more than the terabit-scale switching of datacenter spine ASICs. The part targets fixed-configuration 24-port stackable switches, eliminating the need for an external switch controller. Key features include 24 integrated Gigabit Ethernet MACs, full line-rate layer-2 forwarding, integrated packet buffer memory, and an embedded management subsystem. Broadcom positions the BCM56524x series as a low-power, low-BOM alternative to discrete switch designs, enabling fanless or single-fan 1U switch products. Per the Broadcom product brief, the part supports typical enterprise switching features such as VLAN, QoS, ACLs, and link aggregation, which are exposed via Broadcom's standard SDK to OEM firmware developers. Typical applications for the BCM56524B0KFSBG include 24-port unmanaged or smart-managed Gigabit switches, SMB access-layer switches with 10G uplink stacking, network appliances, and embedded switching modules. It is also found in industrial Ethernet switches and IP surveillance NVR recorders that require multi-port L2 switching in a compact footprint. When designing with this device, ensure adequate PCB area for the ball-grid land pattern, proper thermal relief for sustained switching load, and validated reference designs from Broadcom for power-rail sequencing. Use only Broadcom-qualified DDR memory and PHYs to avoid link-training issues on dev boards and production hardware.
BCM56524B0KFSBLG - 24-Port GbE StrataXGS Switch | Broadcom
The Broadcom BCM56524B0KFSBLG is a member of the StrataXGS III+ family of integrated multilayer Gigabit Ethernet switch fabric ICs, optimized for cost-sensitive enterprise access and SMB switch platforms. The device integrates 24 GbE copper transceivers (SerDes), a high-performance packet processor, and a shared memory switch fabric supporting L2/L3/L4 forwarding at wire speed, all housed in a high-pin-count BGA package designed for managed switch PCB layouts. A Gigabit Ethernet switch IC is a System-on-Chip that combines Media Access Controllers (MACs), PHYs, a packet classifier, forwarding tables, and a switch fabric into a single silicon die. Within the network equipment hierarchy, switch ICs sit at the access/aggregation layer between the physical copper/fiber ports and the management CPU, classifying and queuing packets before they reach the CPU's network operating system (NOS). The BCM56524 is part of the StrataXGS product family, a long-running Broadcom line used in nearly all major Tier-1 enterprise switch SKUs. Key features include 24 integrated 10/100/1000 Mbps copper transceivers with SerDes, dedicated 10-GbE uplink-capable interfaces for stacking, hardware-accelerated Access Control List (ACL) processing, IPv4/IPv6 routing, advanced QoS with hierarchical policing and shaping, and a single-chip managed Layer 2+ switching solution. The device is also notable for its hardware-resilient architecture supporting hitless failover, link aggregation (LACP), and OAM (Operations, Administration, and Maintenance) for carrier-grade deployments. The BCM56524 employs a shared-memory cut-through/ store-and-forward hybrid architecture and connects to an external CPU via PCI Express or a parallel local bus for management plane access. Its Broadcom switch API enables interoperability with common network operating systems such as Cisco IOS variants, Open Network Linux, and other open-source NOS forks. Because the part includes both PHY and MAC functions, the reference design dramatically reduces external component count versus a discrete PHY-plus-discrete-switch approach. Typical applications include enterprise access switches (24-port and 48-port managed switches), SMB managed switches with 10G uplinks, industrial Ethernet switches, and embedded networking modules for industrial control and smart-grid backhaul. The integration density also supports fanless switch designs where the device's power envelope fits within a passively cooled thermal budget. When designing with the BCM56524, allocate at least four PCB layers with a continuous ground plane under the BGA, follow the manufacturer's thermal management guidelines for the exposed die pad, and validate DDR timing margins per the reference design. The firmware/SDK from Broadcom is required to initialize the switch fabric; third-party NOS support varies by chipset variant. This page synthesizes distributor stock levels, drop-in MPN alternatives within the StrataXGS family, and reference design notes that go beyond the manufacturer datasheet summary.
BCM56870A0KFSBG - 3.2T 32x100G Switch | Broadcom
Broadcom BCM56870A0KFSBG is a 3.2 Tbps, 32-port 100G multilayer Ethernet switch controller with a PCIe interface, supplied in the Broadcom KFSB package. The verified distributor records identify this MPN as an Ethernet switch PCIe interface controller and describe a 32x100G multilayer switching configuration. An Ethernet switch controller is a semiconductor that coordinates traffic between multiple network ports, performs packet classification and forwarding, and connects switching silicon to a host or fabric through an interface such as PCIe. Within the network hierarchy, it sits between endpoint transceivers, physical-layer devices, processors, and line-card equipment. This makes it relevant to high-throughput aggregation, top-of-rack, and enterprise switching systems rather than ordinary endpoint Ethernet controllers. The headline configuration combines 3.2 Tbps switching capability with 32 x 100G-class ports. These figures describe the scale of traffic and port density the device targets, but they do not independently establish every electrical or protocol limit. According to the Broadcom and Mouser product records, BCM56870A0KFSBG is associated with the BCM56870 multilayer-switch family and a PCIe interface. Distributor records classify it under Ethernet interface controllers. The part is intended for designs where many high-speed lanes must be aggregated while maintaining a structured switching fabric. Such designs typically require careful lane planning, power delivery, thermal management, clock distribution, signal-integrity control, and protocol-specific firmware. The supplied web data does not provide a complete electrical specification table, pinout, package dimensions, thermal limits, or supported protocol list, so those details must be confirmed against the official Broadcom datasheet before layout or firmware release. Typical uses include 100G Ethernet aggregation equipment, high-port-density switch line cards, top-of-rack designs, and data-center interconnect platforms. In each case, the controller is used with compatible optical or copper transceivers, SerDes infrastructure, packet-processing software, and a host or fabric interface. The device should be selected only when the complete system architecture, lane mapping, power budget, thermal design, and software support have been validated. A key engineering consideration is that high switching throughput does not eliminate the need for careful PCB implementation. Differential pairs, reference planes, connector escape paths, power planes, and thermal paths must be designed together. Because the verified material is distributor-focused and does not expose the full manufacturer specification set, all unreported values remain explicitly marked for validation rather than inferred.
BCM56873A0KFSBG - 2.0T 20x100GbE Ethernet Switch | Broadcom
Broadcom BCM56873A0KFSBG is a 2.0T 20x100GbE multilayer Ethernet switch ASIC designed for high-throughput data-center, cloud, and communications systems. The device provides 20 × 100GbE switching capability in a Broadcom BGA package. Its Ethernet switching architecture is positioned for high-bandwidth aggregation, server-to-fabric, and data-center interconnect designs where aggregate switching performance is the primary design requirement. An Ethernet switch ASIC is a semiconductor that receives Ethernet frames on multiple ports, inspects their destination information, applies configured forwarding or filtering policies, and transmits frames through the appropriate output ports. In the broader networking hierarchy, BCM56873A0KFSBG belongs to the Ethernet switch ASIC, network processor, communications semiconductor, and semiconductor device categories. Its 2.0T switching class is intended to support modern data-center traffic profiles with high port density and aggregate bandwidth. The verified distributor description identifies the BCM56873A0KFSBG as a 2.0T, 20 × 100GbE multilayer switch. The 20-port configuration supports dense high-speed Ethernet interfaces, while the multilayer-switch positioning indicates support for traffic-management functions beyond simple port forwarding. Because the supplied data does not include detailed electrical limits, pin names, clocking details, power characteristics, or software-support information, those parameters remain explicitly marked for datasheet review. Typical deployments include data-center leaf and spine fabrics, cloud infrastructure, high-performance computing interconnects, storage networks, and telecom aggregation equipment. In these applications, switching capacity, port count, and forwarding architecture determine how efficiently multiple 100GbE links can be consolidated. The part should be selected only when the system design is specifically prepared for the BCM56873A0KFSBG package, electrical requirements, reference interfaces, and Broadcom software or firmware ecosystem. The most important design verification steps are to obtain the exact manufacturer datasheet and confirm package dimensions, ball assignments, supply rails, power sequencing, thermal limits, reference-clock requirements, SerDes interfaces, and supported protocols. Do not infer pin compatibility or replacement suitability from distributor descriptions alone. This page separates verified data from missing technical information rather than estimating values that were not supplied.
BCM56990B0KFLGG - 25.6Tb/s Ethernet Switch | Broadcom
The Broadcom BCM56990B0KFLGG is a 25.6-Tb/s multilayer Ethernet switch IC designed for high-density data center and enterprise switching platforms, housed in an LGA (land grid array) package with 8371 terminals in a rectangular grid-array format. A multilayer Ethernet switch IC is a networking silicon device that forwards Layer 2 and Layer 3 packets at line rate, integrating MACs, SERDES, packet processors, and a host CPU interface into a single chip. Within the system hierarchy, the switch IC sits at the core of a switch platform, above PHYs and below system software such as a network operating system (NOS). Key features of the BCM56990 include its 25.6-Tb/s switching capacity, which supports configurations such as 64 ports of 400GbE or high-count 100G/50G breakout modes; the related BCM56990 family member doubles the number of 50G ports from 32 to 64 and introduces 400GbE breakout support. The device integrates a PCIe Gen3 host interface that conforms to the PCIe Gen3 specification and also supports Gen1 and Gen2 operation at x1, x2, or x4 link widths, delivering up to 8.0 GT/s link speed (7.88 Gb/s data rate in each direction) for in-band or out-of-band host management connectivity. Technically, the BCM56990 implements deep packet-buffering and multilayer forwarding architectures typical of Broadcom's StrataXGS switch families, enabling dense leaf/spine topologies, top-of-rack switching, and high-scale aggregation. The 8371-terminal LGA package requires a high-layer-count PCB with dense via-in-pad design and carefully engineered power delivery. Typical applications include hyperscale data center switches, enterprise aggregation switches, white-box switch platforms, and storage networking appliances where 100G/400G port density and full multilayer (L2/L3) forwarding are required. Design consideration: the higher-speed family variants require a higher-performance power delivery network and a faster reference clock (156.25 MHz versus 125 MHz), so clock tree and PDN design must be confirmed against the specific ordering part number before layout reuse. This page synthesizes distributor availability, cross-reference guidance, and practical design notes not found in the manufacturer datasheet, providing engineers with a single citation-ready reference for the BCM56990B0KFLGG.