10AS057H1F34E1HG vs 10AS057H2F34E2LG Vergleich
Detaillierter Direktvergleich von 10AS057H1F34E1HG von Intel und 10AS057H2F34E2LG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
10AS057H2F34E2LG - Arria 10 SX SoC FPGA 570K LE, Dual ARM Cortex-A9 | Intel
10AS057H2F34E2LG ✓ AktivSpezifikationsvergleich
| Parameter | 10AS057H1F34E1HG | 10AS057H2F34E2LG |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3.300,00 | $2.524,10 |
| Family | Arria 10 SX | Arria 10 SX |
| Series | 10AS057 | — |
| Logic Elements | 570 K | 570,000 |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum HPS Core Frequency | 1.5 GHz | — |
| Gehäuse | 1152-FBGA, FC (35x35 mm) | 1152-ball FCBGA (F34, 35x35 mm) |
| Pin/Ball Count | 1152 | — |
| I/O Count | 492 user I/O | — |
| Process Technology | 20 nm | — |
| Transceiver Data Rate (max) | 17.7 Gbps | — |
| Embedded Memory | [DATA_NEEDED: total Mbits] | — |
| DSP Blocks | [DATA_NEEDED: count] | — |
| Memory Controller | Hard DDR3/DDR4 controller in HPS and FPGA fabric | Hard DDR4 controller |
| PCIe Hard IP | PCIe Gen2/Gen3 x1/x2/x4 | PCI Express Gen3 |
| Betriebstemperatur | -40C to +100C (industrial) | 0C to +100C TJ |
| Montageart | Surface Mount (FCBGA) | Surface Mount (BGA) |
| RoHS-Status | Compliant | Non-compliant (per Hotenda listing) |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | [DATA_NEEDED: MSL level] | — |
| Product Type | — | System-on-Chip (SoC) FPGA |
| Processor Subsystem | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| Hard Processor Core Clock | — | 1.5 GHz |
| User I/O Count | — | 492 |
| Transceiver Channels | — | 24 (up to 17.4 Gbps backplane) |
| Core Voltage | — | 0.9 V |
| Speed Grade | — | -E2 |
| Configuration | — | AS / PS / FPP / JTAG |
| MSL-Level | — | [DATA_NEEDED: MSL] |