10AS057K2F35E2SG vs 10AS057K2F35E2LG Vergleich
Detaillierter Direktvergleich von 10AS057K2F35E2SG von Intel und 10AS057K2F35E2LG von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10AS057K2F35E2SG | 10AS057K2F35E2LG |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $2.304,55 | $3.450,00 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570,000 |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count for 570K LE Arria 10 SX] | — |
| Embedded Memory (M20K blocks) | [DATA_NEEDED: M20K count for 570K LE] | — |
| Embedded Memory (MLAB bits) | [DATA_NEEDED: MLAB bits for 570K LE] | — |
| DSP Blocks (18x19 Multipliers) | 1,568 | — |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 1.5 GHz | 1.5 GHz |
| Maximum User I/O | 396 | — |
| Transceiver Count (GX/SX) | 24 | — |
| Transceiver Max Data Rate | 17.4 Gbps | — |
| Hard PCIe Blocks | Gen2/Gen3 x4/x8 IP | — |
| Gehäuse | 1152-FBGA, FC (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | E2 (mid-tier) | E2 (commercial/extended) |
| Betriebstemperatur | [DATA_NEEDED: commercial/industrial grade range] | -40C to +100C (extended-industrial screening) |
| Process Node | 20 nm (TSMC) | TSMC 20 nm |
| Montageart | Surface Mount (FCBGA) | — |
| RoHS-Status | Compliant (lead-free) | Compliant |
| MSL-Level | [DATA_NEEDED: MSL rating] | — |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| DSP Blocks | — | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| Transceivers | — | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | — | Gen3 x4 (rootport/endpoint) |
| User I/Os | — | 396 |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| Lead-Free | — | Yes |