10AS057K2F35E2SG vs 10AS057K2F35E2LG Сравнение
Подробное сравнение бок о бок 10AS057K2F35E2SG от Intel и 10AS057K2F35E2LG от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | 10AS057K2F35E2SG | 10AS057K2F35E2LG |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $2.304,55 | $3.450,00 |
| Family | Arria 10 SX SoC FPGA | Arria 10 SX SoC FPGA |
| Logic Elements | 570,000 | 570,000 |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count for 570K LE Arria 10 SX] | — |
| Embedded Memory (M20K blocks) | [DATA_NEEDED: M20K count for 570K LE] | — |
| Embedded Memory (MLAB bits) | [DATA_NEEDED: MLAB bits for 570K LE] | — |
| DSP Blocks (18x19 Multipliers) | 1,568 | — |
| HPS Core | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 1.5 GHz | 1.5 GHz |
| Maximum User I/O | 396 | — |
| Transceiver Count (GX/SX) | 24 | — |
| Transceiver Max Data Rate | 17.4 Gbps | — |
| Hard PCIe Blocks | Gen2/Gen3 x4/x8 IP | — |
| Корпус | 1152-FBGA, FC (35x35 mm) | 1152-ball FCBGA, 35 mm x 35 mm, 1.0 mm pitch |
| Speed Grade | E2 (mid-tier) | E2 (commercial/extended) |
| Рабочая температура | [DATA_NEEDED: commercial/industrial grade range] | -40C to +100C (extended-industrial screening) |
| Process Node | 20 nm (TSMC) | TSMC 20 nm |
| Тип монтажа | Surface Mount (FCBGA) | — |
| Статус RoHS | Compliant (lead-free) | Compliant |
| Уровень MSL | [DATA_NEEDED: MSL rating] | — |
| HPS Cores | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| DSP Blocks | — | [DATA_NEEDED: 18x19 multiplier count] |
| Embedded Memory (M20K) | — | [DATA_NEEDED: M20K block count and total bits] |
| Transceivers | — | Up to 24 channels, up to 17.4 Gbps |
| PCIe Hard IP | — | Gen3 x4 (rootport/endpoint) |
| User I/Os | — | 396 |
| Configuration | — | SRAM-based, partial reconfiguration, SEU mitigation, ECC |
| Memory Interfaces | — | DDR3/DDR4 with hard PHY (HPS + FPGA) |
| Lead-Free | — | Yes |