10CL055YU484I7G vs 10CL055ZF484I8G Vergleich
Detaillierter Direktvergleich von 10CL055YU484I7G von Altera und 10CL055ZF484I8G von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 10CL055YU484I7G | 10CL055ZF484I8G |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $35,10 | $54,49 |
| Family | Cyclone 10 LP | Cyclone 10 LP |
| Logic Elements | 55,856 | — |
| Embedded Memory Bits | 2,396,160 bits | — |
| M9K Memory Blocks | 260 | — |
| Maximum User I/Os | 321 | — |
| DSP Blocks (18x18 multipliers) | 156 | — |
| PLLs | 4 | 4 |
| Global Clock Networks | 20 | — |
| Process Technology | 60 nm low-power CMOS | — |
| Gehäuse | 484-ball UBGA (Ultra FineLine BGA), 19 mm x 19 mm | 484-ball FBGA (F484) |
| Speed Grade | -7 (I7, industrial) | — |
| Betriebs-Sperrschichttemperatur | -40C to +100C | — |
| Core Voltage (VCCINT) | 1.0V (typical), 1.1V nominal | — |
| I/O Voltage (VCCIO) | 1.2V to 3.3V (bank-dependent) | — |
| Configuration Modes | JTAG, AS, PS, FPP | — |
| LVDS Data Rate | Up to 875 Mbps per channel | — |
| RoHS-Status | Compliant | Compliant |
| MSL-Level | 3 (per JEDEC J-STD-020) | 3 |
| Logic Elements (LE) | — | 55,856 |
| Configurable Logic Blocks (CLB) | — | 3,491 |
| Embedded Memory | — | 2,396,160 bits (2,340 Kbit) |
| Embedded Multipliers (18x18) | — | 156 |
| Maximum User I/O | — | 321 |
| Process Node | — | 20 nm |
| Betriebstemperatur | — | -40C to +100C (Industrial) |
| Montageart | — | Surface Mount |
| Supply Voltage (Core) | — | [DATA_NEEDED: core voltage] |
| Configuration Memory | — | SRAM-based (volatile, external flash required) |
| I/O Standards Supported | — | LVDS, LVTTL, LVCMOS, SSTL, HSTL |
| External Memory Interface | — | DDR3, DDR3L, LPDDR2 |