2EDN7434RXTMA1 vs 2EDN7524GXTMA1 Vergleich
Detaillierter Direktvergleich von 2EDN7434RXTMA1 von Infineon und 2EDN7524GXTMA1 von Infineon. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Infineon
2EDN7524GXTMA1 - 5A Dual Low-Side Gate Driver for MOSFET/GaN | Infineon
2EDN7524GXTMA1 ✓ AktivSpezifikationsvergleich
| Parameter | 2EDN7434RXTMA1 | 2EDN7524GXTMA1 |
|---|---|---|
| Marke | Infineon | Infineon |
| Kategorie | Power MOSFET Drivers | Power MOSFET Drivers |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,34 | $0,82 |
| Manufacturer | Infineon Technologies | — |
| Part Family | EiceDRIVER 2EDN | — |
| Driver Configuration | Dual-channel low-side | — |
| Number of Drivers | 2 | — |
| Peak Output Current | 5 A (source/sink) | — |
| Rated Output Current | 4 A | — |
| Output Resistance (Low) | [DATA_NEEDED: output resistance Ron low] | — |
| Output Resistance (High) | [DATA_NEEDED: output resistance Ron high] | — |
| Propagation Delay (Typ.) | 19 ns | — |
| Input Logic Compatibility | LV-TTL, non-inverting | — |
| Absolute Max Input Voltage | -12 V to +22 V | — |
| Supply Voltage Range | [DATA_NEEDED: VDD range] | — |
| Gehäuse | PG-TSSOP-8 (3.0 x 3.0 mm) | PG-WSON-8-1 (3 mm x 3 mm) with exposed thermal pad |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature] | — |
| RoHS-Status | Compliant | Compliant |
| MSL-Level | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL level] |
| Active Output Voltage Clamping | Yes | — |
| Product Type | — | Low-side gate driver IC |
| Number of Channels | — | 2 (dual) |
| Drive Current (Source/Sink) | — | 5 A peak |
| Input Logic | — | Non-inverting, TTL / 3.3 V CMOS-compatible |
| Input Voltage Tolerance | — | -10 V to +20 V on logic pins |
| Supply Voltage (VCC) | — | 4.5 V to 20 V [DATA_NEEDED: exact range] |
| Propagation Delay | — | 20 ns typical [DATA_NEEDED: exact figure] |
| Channel-to-Channel Delay Matching | — | 1 ns |
| Anstiegszeit | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Abfallzeit | — | 5 ns typical [DATA_NEEDED: exact test condition] |
| Output Stage | — | Rail-to-rail, separate source/sink |
| UVLO Protection | — | Yes |
| Betriebstemperatur | — | -40 C to +125 C |
| Target Devices | — | Standard MOSFETs, superjunction MOSFETs, GaN HEMTs |