5CSEBA2U19I7SN vs 5CSEBA2U23A7N Vergleich

Detaillierter Direktvergleich von 5CSEBA2U19I7SN von Altera und 5CSEBA2U23A7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter 5CSEBA2U19I7SN 5CSEBA2U23A7N
Marke Altera Intel
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $65,96 $99,50
Device Type Cyclone V SE FPGA system-on-chip (SoC) —
Processor Core Single ARM Cortex-A9 MPCore —
Debug Technology CoreSight —
Logic Elements 25K logic elements 25,000 LE
Device Frequency 800 MHz —
I/O Count 240 I/O —
Gehäuse 484-UBGA 672-UBGA (23x23 mm)
Package Dimensions 19 mm x 19 mm —
FPGA Architecture Cyclone V SE —
Montageart Surface mount Surface Mount (BGA)
Integrated Processor Yes —
Logic Technology Field-programmable gate array —
Device Category Embedded system-on-chip FPGA —
RoHS-Status unknown Compliant (per ampheo listing)
REACH Status unknown —
AEC-Q100 Status unknown —
Betriebstemperaturbereich [DATA_NEEDED: operating temperature range] —
Versorgungsspannung [DATA_NEEDED: supply voltage range] —
Transceiver Count [DATA_NEEDED: transceiver count] —
Speichertyp [DATA_NEEDED: memory type and capacity] —
Family — Cyclone V SE SoC FPGA
MPN Code — 5CSEBA2U23A7N (Cyclone V SE A2, U23 package)
Hard Processor System (HPS) — Dual-core ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Frequency — 700 MHz
Process Technology — 28 nm low-power
User I/O — 188
Speed Grade — 7
Temperature Grade — A (Commercial, 0C to +85C) [DATA_NEEDED: exact junction range]
MSL-Level — [DATA_NEEDED: MSL level]
Operating Voltage (Core) — 1.1 V (typical FPGA core, multi-rail HPS)
Configuration Scheme — HPS-boot of FPGA fabric via configuration QSPI
Embedded Memory — M10K blocks (count [DATA_NEEDED: exact M10K/M20K count])
DSP Blocks — Variable-precision DSP (count [DATA_NEEDED: exact count])
PLLs — Fractional PLLs (count [DATA_NEEDED: exact PLL count])

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