5CSEBA4U19I7LN vs 5CSEBA5U19C7N Vergleich
Detaillierter Direktvergleich von 5CSEBA4U19I7LN von Intel und 5CSEBA5U19C7N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5CSEBA4U19I7LN | 5CSEBA5U19C7N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $168,00 | $99,20 |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Logic Elements | 40K | 85,000 |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 925 MHz | 800 MHz per core |
| FPGA Logic Performance | up to 925 MHz DSP / 300 MHz logic | — |
| Embedded Memory (M10K) | [DATA_NEEDED: total M10K bits] | — |
| DSP Blocks (18x18 Multipliers) | 56 | — |
| PLLs | [DATA_NEEDED: PLL count per family datasheet] | — |
| Memory Controller | DDR2/DDR3/LPDDR2 with ECC (hardened in HPS) | — |
| HPS Peripherals | UART, SPI, I2C, USB 2.0 OTG, EMAC, SD/MMC, NAND, GPIO | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| Gehäuse | 484-pin UFBGA (19x19 mm, 0.8 mm pitch) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Process Technology | TSMC 28 nm low-power | — |
| Operating Temperature (Industrial) | -40C to +100C (I7 grade, inferred from MPN suffix) | — |
| Supply Voltage (core) | 1.1 V typical (Cyclone V family) | — |
| RoHS-Status | Compliant | — |
| Configuration Scheme | Serial (EPCS) or Quad-Serial Flash | — |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Betriebstemperatur | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| DSP Blocks | — | Variable-precision, 18x18 / 27x27 multipliers |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| MSL-Level | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |