5CSXFC6C6U23I7NTS vs 5CSXFC6C6U23C8N Vergleich
Detaillierter Direktvergleich von 5CSXFC6C6U23I7NTS von Intel und 5CSXFC6C6U23C8N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
5CSXFC6C6U23C8N - Cyclone V SX SoC FPGA, 110K LE, ARM Cortex-A9 | Intel
5CSXFC6C6U23C8N ✓ AktivSpezifikationsvergleich
| Parameter | 5CSXFC6C6U23I7NTS | 5CSXFC6C6U23C8N |
|---|---|---|
| Marke | Intel | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $416,50 | $445,00 |
| Family | Cyclone V SX SoC FPGA | Cyclone V SX (SoC FPGA) |
| Logic Elements | 110 K | 110,000 |
| Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Processor Clock Frequency | 925 MHz | — |
| Process Technology | 28 nm low-power | 28 nm low-power (TSMC) |
| Gehäuse | 672-pin UBGA (U23) 23x23 mm | 672-pin UFBGA (UBGA), 23x23 mm |
| Montageart | Surface Mount (BGA) | Surface Mount (BGA) |
| Configuration | JTAG / Active Serial / Passive Serial | — |
| Hard Memory Controller | DDR2 / DDR3 / LPDDR2 | — |
| Embedded Memory | M20K (20 Kb) blocks | M10K blocks (total Kbits [DATA_NEEDED: total embedded memory Kbits]) |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP (number not specified in retrieved data) |
| Betriebstemperatur | -40 C to +100 C (Industrial, I7) | -40C to +100C (industrial grade, code C) |
| High-Speed Transceivers | Integrated (per Cyclone V SX family) | — |
| RoHS-Status | Compliant | Compliant |
| Lead-Free / Halogen-Free | Yes / [DATA_NEEDED: halogen-free status] | Yes (lead-free BGA; halogen status [DATA_NEEDED: halogen-free yes/no]) |
| Series | — | Cyclone V SX |
| Architecture | — | MCU + FPGA (Hard Processor System + FPGA fabric) |
| Core Voltage | — | 1.1 V |
| Hard Processor System (HPS) | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| Processor Maximum Frequency | — | 600 MHz |
| HPS L1 Cache | — | 32 KB instruction + 32 KB data per core |
| HPS L2 Cache | — | 512 KB shared |
| Transceivers | — | Up to 3.125 Gbps integrated transceivers |
| Maximum User I/O | — | 145 user I/O (per DigChip summary; full count per package [DATA_NEEDED: package pinout max user I/O]) |
| Memory Controller | — | Hard controller supporting DDR2, DDR3, LPDDR2 |
| MSL-Level | — | 3 (per JEDEC J-STD-020, typical for large BGA) |
| Speed Grade | — | C8 (commercial speed grade 8) |
| Lifecycle | — | Active (Cyclone V family in production) |