5M1270ZT144C4N vs 5M1270ZT144C5N Vergleich
Detaillierter Direktvergleich von 5M1270ZT144C4N von Altera und 5M1270ZT144C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktivSpezifikationsvergleich
| Parameter | 5M1270ZT144C4N | 5M1270ZT144C5N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,49 | $12,45 |
| Family | MAX V CPLD | — |
| Logic Elements | 1270 | 1270 |
| Macrocells | 980 | 980 |
| User I/O Pins | 114 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Pin-to-Pin Propagation Delay (tPD) | 8.1 ns | 6.2 ns |
| Maximum Internal Frequency | 247.5 MHz | 118.3 MHz |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) | — |
| Process Technology | 0.18 um CMOS | — |
| Configuration Memory | Non-volatile Flash | Flash (non-volatile, in-system programmable) |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable | JTAG in-system programmable (Altera Quartus II) |
| User Flash Memory (UFM) | Yes (on-chip, non-volatile data storage) | 8 Kbits |
| Gehäuse | 144-pin TQFP (22 mm x 22 mm, 0.5 mm pitch) | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (0C to +85C) | — |
| RoHS-Status | Compliant | Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX V |
| User I/Os | — | 114 |
| Internal Frequency (typical) | — | 201 MHz |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Betriebstemperatur | — | 0 C to +85 C (commercial grade) |