5M1270ZT144C4N vs 5M1270ZT144C5N Comparaison
Comparaison détaillée côte à côte de 5M1270ZT144C4N par Altera et 5M1270ZT144C5N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ ActifComparaison des spécifications
| Paramètre | 5M1270ZT144C4N | 5M1270ZT144C5N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,49 | $12,45 |
| Family | MAX V CPLD | — |
| Logic Elements | 1270 | 1270 |
| Macrocells | 980 | 980 |
| User I/O Pins | 114 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Pin-to-Pin Propagation Delay (tPD) | 8.1 ns | 6.2 ns |
| Maximum Internal Frequency | 247.5 MHz | 118.3 MHz |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) | — |
| Process Technology | 0.18 um CMOS | — |
| Configuration Memory | Non-volatile Flash | Flash (non-volatile, in-system programmable) |
| Programming Interface | JTAG (IEEE 1149.1) - In-System Programmable | JTAG in-system programmable (Altera Quartus II) |
| User Flash Memory (UFM) | Yes (on-chip, non-volatile data storage) | 8 Kbits |
| Boîtier | 144-pin TQFP (22 mm x 22 mm, 0.5 mm pitch) | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Type de montage | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (0C to +85C) | — |
| Statut RoHS | Compliant | Compliant |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | MAX V |
| User I/Os | — | 114 |
| Internal Frequency (typical) | — | 201 MHz |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Température de fonctionnement | — | 0 C to +85 C (commercial grade) |