5M1270ZT144I5 vs 5M1270ZT144C5N Vergleich
Detaillierter Direktvergleich von 5M1270ZT144I5 von Intel und 5M1270ZT144C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ AktivSpezifikationsvergleich
| Parameter | 5M1270ZT144I5 | 5M1270ZT144C5N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,95 | $12,45 |
| Family | MAX V | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 980 | — |
| User I/Os | 114 | 114 |
| Logic Array Blocks (LABs) | 8 | — |
| Internal Frequency | 201 MHz | — |
| Propagation Delay (tPD) | 10 ns | — |
| Core Supply Voltage | 1.8 V | — |
| I/O Voltage Support | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | — |
| Gehäuse | TQFP-144 (22 × 22 mm, 0.5 mm pitch) | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | -40 °C to +100 °C (Industrial) | 0 C to +85 C (commercial grade) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | Flash (non-volatile, in-system programmable) |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG in-system programmable (Altera Quartus II) |
| RoHS-Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Series | — | MAX V |
| Logic Elements | — | 1270 |
| Macrocells | — | 980 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |