5M160ZE64C5N vs 5M40ZE64A5N Vergleich
Detaillierter Direktvergleich von 5M160ZE64C5N von Altera und 5M40ZE64A5N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5M160ZE64C5N | 5M40ZE64A5N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,95 | $2,18 |
| Series | MAX V | MAX V |
| Device Family | MAX V (5M160Z) | MAX V (5M40Z) |
| Logic Elements (LE) | 160 | 40 |
| Macrocells | 128 | — |
| User I/O Pins | 54 | — |
| Maximum Operating Frequency (fMAX) | 118.3 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) | — |
| Configuration Memory | Non-volatile Flash | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | 4 Kbit |
| Gehäuse | 64-pin EQFP (E64) with exposed pad | EQFP-64 (E64, 10x10 mm, 0.5 mm pitch) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0°C to +85°C (commercial) | — |
| Programming Interface | JTAG (IEEE 1149.1) / In-system | — |
| RoHS-Status | Compliant | Compliant (Pb-free) |
| MSL-Level | 3 | 3 (168 hours) |
| Logic Array Blocks (LAB) | — | 2 (20 LEs each) |
| Maximum User I/O | — | 30 |
| Pin-to-Pin Delay (tPD) | — | 5 ns (commercial speed grade) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.2 V to 3.3 V (4 banks) |
| Betriebstemperaturbereich | — | 0 C to +85 C (commercial) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | On-chip non-volatile flash (instant-on) |