5M240ZM68I5N vs EPM570ZM100I8N Vergleich
Detaillierter Direktvergleich von 5M240ZM68I5N von Intel und EPM570ZM100I8N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | 5M240ZM68I5N | EPM570ZM100I8N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $1,25 | $16,50 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | EPM570Z |
| Logic Elements | 240 | 570 |
| Number of Macrocells | 192 | 440 |
| Propagation Delay (tPD) | 7.5 ns | 9 ns |
| Configuration Memory | Nonvolatile Flash | — |
| Package Type | TFBGA-68 | — |
| Number of Terminals | 68 (ball) | — |
| Package Code | TFBGA | — |
| Form of Terminal | Ball | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Industrial | — |
| JTAG Interface | TMS, TDI, TDO, TCK (Bank 1) | — |
| Programming Method | JTAG / in-system programmable | — |
| Versorgungsspannung | [DATA_NEEDED: VCCINT and VCCIO levels] | — |
| I/O Standards | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) | — |
| Montageart | Surface Mount | — |
| RoHS-Status | Compliant | — |
| Lead Free | Yes | — |
| Device Family | — | MAX II |
| Number of Logic Array Blocks (LABs) | — | 57 |
| User I/Os | — | 76 |
| Maximum Operating Frequency | — | 152 MHz |
| Operating Supply Voltage (Core) | — | 1.8 V |
| Programming Technology | — | Flash, non-volatile |
| In-System Programmability (ISP) | — | Yes (JTAG) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| Betriebstemperaturbereich | — | -40 C to +85 C (Industrial) |
| Montagestil | — | SMD/SMT |
| Gehäuse / Bauform | — | 100-ball FineLine BGA (MBGA, 0.8 mm pitch) |
| Packaging | — | Tray |