5M240ZM68I5N vs EPM570ZM100I8N 比較
詳細な並列比較: 5M240ZM68I5N メーカー: Intel および EPM570ZM100I8N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | 5M240ZM68I5N | EPM570ZM100I8N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $1.25 | $16.50 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Series | MAX V | EPM570Z |
| Logic Elements | 240 | 570 |
| Number of Macrocells | 192 | 440 |
| Propagation Delay (tPD) | 7.5 ns | 9 ns |
| Configuration Memory | Nonvolatile Flash | — |
| Package Type | TFBGA-68 | — |
| Number of Terminals | 68 (ball) | — |
| Package Code | TFBGA | — |
| Form of Terminal | Ball | — |
| Package Shape | Square | — |
| Operating Temperature Grade | Industrial | — |
| JTAG Interface | TMS, TDI, TDO, TCK (Bank 1) | — |
| Programming Method | JTAG / in-system programmable | — |
| 電源電圧 | [DATA_NEEDED: VCCINT and VCCIO levels] | — |
| I/O Standards | Multiple (LVTTL, LVCMOS, SSTL, etc., per MAX V doc; PCI and 1.2 V LVCMOS excluded for JTAG pins) | — |
| 実装タイプ | Surface Mount | — |
| RoHS ステータス | Compliant | — |
| Lead Free | Yes | — |
| Device Family | — | MAX II |
| Number of Logic Array Blocks (LABs) | — | 57 |
| User I/Os | — | 76 |
| Maximum Operating Frequency | — | 152 MHz |
| Operating Supply Voltage (Core) | — | 1.8 V |
| Programming Technology | — | Flash, non-volatile |
| In-System Programmability (ISP) | — | Yes (JTAG) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| 動作温度範囲 | — | -40 C to +85 C (Industrial) |
| 実装スタイル | — | SMD/SMT |
| パッケージ / ケース | — | 100-ball FineLine BGA (MBGA, 0.8 mm pitch) |
| Packaging | — | Tray |