5M240ZT100I5N vs 5M240ZT100C5N Vergleich

Detaillierter Direktvergleich von 5M240ZT100I5N von Altera und 5M240ZT100C5N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter 5M240ZT100I5N 5M240ZT100C5N
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Aktiv Aktiv
Lagerstatus In Stock In Stock
Stückpreis (USD) $4,81 $4,98
Family MAX V MAX V
Series 5M240Z —
Device Type CPLD (Complex Programmable Logic Device) —
Logic Elements 240 —
Macrocells 192 192
User Flash Memory 8 Kbit 8 Kbits
Maximum User I/O 114 —
User I/O Pins (per datasheet) 79 —
Anzahl der Pins 100 —
Package Type TQFP-100 (T100) —
Package Body Size 14 x 14 mm —
Lead Pitch 0.50 mm —
Core Voltage (VCCINT) 1.8 V —
I/O Bank Voltage (VCCIO) 1.2 V to 3.3 V (bank-dependent) —
Speed Grade -5 —
Maximum Internal Frequency 118.3 MHz 118.3 MHz
Pin-to-Pin Delay (tPD1) 7.5 ns (per datasheet header) —
Betriebstemperatur -40 C to +100 C (Industrial) 0C to +85C (commercial grade)
Programming Interface JTAG (IEEE 1149.1) / ISP JTAG (IEEE 1149.1)
Configuration Memory Non-volatile flash (instant-on) Internal flash (non-volatile, instant-on)
Montageart Surface Mount Surface Mount
Lead-Free / RoHS Yes (LEAD FREE per datasheet header) —
MSL-Level [DATA_NEEDED: MSL Level] [DATA_NEEDED: MSL level]
AEC-Q100 Automotive Not qualified (Industrial grade) —
Logic Elements (LEs) — 240
User I/Os — 79
Pin-to-Pin Logic Delay (Tpd1) — 7.5 ns (per distributor classification)
Operating Voltage (VCCINT) — 3.3 V (internal 1.8 V core derived)
I/O Bank Voltages Supported — 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL
Gehäuse — TQFP-100 (14 x 14 mm, 0.5 mm pitch)
RoHS-Status — Compliant (per LCSC listing)

Datenblätter & Ressourcen

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